The use of Verilog language, a 4-bit counter design.

yiwei\db\logic_util_heursitic.dat
.....\..\prev_cmp_yiwei.asm.qmsg
.....\..\prev_cmp_yiwei.fit.qmsg
.....\..\prev_cmp_yiwei.map.qmsg
.....\..\prev_cmp_yiwei.qmsg
.....\..\prev_cmp_yiwei.sta.qmsg
.....\..\yiwei.asm.qmsg
.....\..\yiwei.asm.rdb
.....\..\yiwei.asm_labs.ddb
.....\..\yiwei.cbx.xml
.....\..\yiwei.cmp.bpm
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.....\..\yiwei.cmp.kpt
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.....\..\yiwei.cmp.rdb
.....\..\yiwei.cmp_merge.kpt
.....\..\yiwei.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.....\..\yiwei.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd
.....\..\yiwei.db_info
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.....\..\yiwei.fit.qmsg
.....\..\yiwei.hier_info
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.....\..\yiwei.lpc.html
.....\..\yiwei.lpc.rdb
.....\..\yiwei.lpc.txt
.....\..\yiwei.map.bpm
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.....\..\yiwei.map.kpt
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.....\..\yiwei.map.qmsg
.....\..\yiwei.map_bb.cdb
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.....\..\yiwei.pre_map.cdb
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.....\..\yiwei.rtlv.hdb
.....\..\yiwei.rtlv_sg.cdb
.....\..\yiwei.rtlv_sg_swap.cdb
.....\..\yiwei.sgdiff.cdb
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.....\..\yiwei.sld_design_entry.sci
.....\..\yiwei.sld_design_entry_dsc.sci
.....\..\yiwei.smart_action.txt
.....\..\yiwei.sta.qmsg
.....\..\yiwei.sta.rdb
.....\..\yiwei.sta_cmp.8_slow_1200mv_85c.tdb
.....\..\yiwei.syn_hier_info
.....\..\yiwei.tiscmp.fast_1200mv_0c.ddb
.....\..\yiwei.tiscmp.slow_1200mv_0c.ddb
.....\..\yiwei.tiscmp.slow_1200mv_85c.ddb
.....\..\yiwei.tis_db_list.ddb
.....\..\yiwei.tmw_info
.....\incremental_db\compiled_partitions\yiwei.root_partition.cmp.cdb
.....\..............\...................\yiwei.root_partition.cmp.dfp
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.....\..............\...................\yiwei.root_partition.cmp.kpt
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.....\..............\...................\yiwei.root_partition.map.kpt
.....\..............\README
.....\yiwei.asm.rpt
.....\yiwei.done
.....\yiwei.fit.rpt
.....\yiwei.fit.smsg
.....\yiwei.fit.summary
.....\yiwei.flow.rpt
.....\yiwei.map.rpt
.....\yiwei.map.summary
.....\yiwei.pin
.....\yiwei.qpf
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.....\yiwei.qws
.....\yiwei.sof
.....\yiwei.sta.rpt
.....\yiwei.sta.summary
.....\yiwei.v
.....\yiwei.v.bak
.....\incremental_db\compiled_partitions
.....\db
.....\incremental_db
yiwei

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