Learning asynchronous reset, synchronous release of circuit modeling approach. Asynchronous reset, synchronous release of many of the specific design, the key is how to ensure simultaneous release of the reset signal. The design of this case is the release of the reset signal when the sampling clock with the system, and then register the asynchronous reset signal to reset the terminal.

Example-4-17
............\asyn_rst
............\........\asyn_rst.prd
............\........\asyn_rst.prj
............\........\asyn_rst.v
............\........\rev_1
............\........\.....\asyn_rst.edn
............\........\.....\asyn_rst.prf
............\........\.....\asyn_rst.srm
............\........\.....\asyn_rst.srr
............\........\.....\asyn_rst.srs
............\........\.....\asyn_rst.tlg
............\........\.....\AutoConstraint_asyn_rst.sdc
............\........\.....\generic.srd
............\........\.....\syntmp
............\........\.....\......\asyn_rst.plg
............\asyn_rst_syn_release
............\....................\asyn_rst_syn_release.v
............\source
............\syn_rst
............\.......\rev_2
............\.......\.....\AutoConstraint_syn_rst.sdc
............\.......\.....\generic.srd
............\.......\.....\par_1
............\.......\.....\syntmp
............\.......\.....\......\syn_rst.msg
............\.......\.....\......\syn_rst.plg
............\.......\.....\syn_rst.edn
............\.......\.....\syn_rst.prf
............\.......\.....\syn_rst.srm
............\.......\.....\syn_rst.srr
............\.......\.....\syn_rst.srs
............\.......\.....\syn_rst.tlg
............\.......\sim
............\.......\syn_rst.prd
............\.......\syn_rst.prj
............\.......\syn_rst.v
............\~$示例说明.doc
............\示例说明.doc

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