This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente in the years 1993-2002.1 The text has undergone a major revision in order to be suitable for use in the elective course VLSI System Design.2 Before presenting the syntax of the language, first some general background information on top-down design and the design trajectory is presented. The document then continues with a short explanation of the simulation principles that the language assumes. The last part of the document deals with synthesis issues.

44317447-Vhdl-Sim-Syn.pdf

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