HDLC-based Verilog decoder. Output of an external differential output 485.

hdlc_encode\db\hdlc_encode.asm.qmsg
...........\..\hdlc_encode.cbx.xml
...........\..\hdlc_encode.cmp.bpm
...........\..\hdlc_encode.cmp.cdb
...........\..\hdlc_encode.cmp.ecobp
...........\..\hdlc_encode.cmp.hdb
...........\..\hdlc_encode.cmp.logdb
...........\..\hdlc_encode.cmp.rdb
...........\..\hdlc_encode.cmp.tdb
...........\..\hdlc_encode.cmp0.ddb
...........\..\hdlc_encode.db_info
...........\..\hdlc_encode.eco.cdb
...........\..\hdlc_encode.eda.qmsg
...........\..\hdlc_encode.fit.qmsg
...........\..\hdlc_encode.hier_info
...........\..\hdlc_encode.hif
...........\..\hdlc_encode.map.bpm
...........\..\hdlc_encode.map.cdb
...........\..\hdlc_encode.map.ecobp
...........\..\hdlc_encode.map.hdb
...........\..\hdlc_encode.map.logdb
...........\..\hdlc_encode.map.qmsg
...........\..\hdlc_encode.map_bb.cdb
...........\..\hdlc_encode.map_bb.hdb
...........\..\hdlc_encode.map_bb.hdbx
...........\..\hdlc_encode.map_bb.logdb
...........\..\hdlc_encode.pre_map.cdb
...........\..\hdlc_encode.pre_map.hdb
...........\..\hdlc_encode.psp
...........\..\hdlc_encode.root_partition.cmp.atm
...........\..\hdlc_encode.root_partition.cmp.dfp
...........\..\hdlc_encode.root_partition.cmp.hdbx
...........\..\hdlc_encode.root_partition.cmp.logdb
...........\..\hdlc_encode.root_partition.cmp.rcf
...........\..\hdlc_encode.root_partition.map.atm
...........\..\hdlc_encode.root_partition.map.hdbx
...........\..\hdlc_encode.root_partition.map.info
...........\..\hdlc_encode.rtlv.hdb
...........\..\hdlc_encode.rtlv_sg.cdb
...........\..\hdlc_encode.rtlv_sg_swap.cdb
...........\..\hdlc_encode.sgdiff.cdb
...........\..\hdlc_encode.sgdiff.hdb
...........\..\hdlc_encode.signalprobe.cdb
...........\..\hdlc_encode.sld_design_entry.sci
...........\..\hdlc_encode.sld_design_entry_dsc.sci
...........\..\hdlc_encode.smp_dump.txt
...........\..\hdlc_encode.syn_hier_info
...........\..\hdlc_encode.tan.qmsg
...........\..\hdlc_encode.tis_db_list.ddb
...........\..\hdlc_encode.tmw_info
...........\..\prev_cmp_hdlc_encode.asm.qmsg
...........\..\prev_cmp_hdlc_encode.eda.qmsg
...........\..\prev_cmp_hdlc_encode.fit.qmsg
...........\..\prev_cmp_hdlc_encode.map.qmsg
...........\..\prev_cmp_hdlc_encode.qmsg
...........\..\prev_cmp_hdlc_encode.tan.qmsg
...........\hdlc_encode.asm.rpt
...........\hdlc_encode.done
...........\hdlc_encode.eda.rpt
...........\hdlc_encode.fit.rpt
...........\hdlc_encode.fit.smsg
...........\hdlc_encode.fit.summary
...........\hdlc_encode.flow.rpt
...........\hdlc_encode.map.rpt
...........\hdlc_encode.map.smsg
...........\hdlc_encode.map.summary
...........\hdlc_encode.pin
...........\hdlc_encode.pof
...........\hdlc_encode.qpf
...........\hdlc_encode.qsf
...........\hdlc_encode.qws
...........\hdlc_encode.sof
...........\hdlc_encode.tan.rpt
...........\hdlc_encode.tan.summary
...........\hdlc_encode.v
...........\hdlc_encode.v.bak
...........\simulation\hdlc_encode.cr.mti
...........\..........\hdlc_encode.mpf
...........\..........\modelsim\111111
...........\..........\........\altera_mf.v
...........\..........\........\cyclone_atoms.v
...........\..........\........\hdlc_encode.cr.mti
...........\..........\........\hdlc_encode.mpf
...........\..........\........\hdlc_encode.sft
...........\..........\........\hdlc_encode.vo
...........\..........\........\hdlc_encode_modelsim.xrf
...........\..........\........\hdlc_encode_v.sdo
...........\..........\........\top.v
...........\..........\........\transcript
...........\..........\........\vsim.wlf
...........\..........\........\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
...........\..........\........\....\..........................................\_primary.dat
...........\..........\........\....\..........................................\_primary.vhd
...........\..........\........\....\.c@y@c@l@o@n@e_@p@r@i@m_@d@f@f@e\verilog.asm
...........\..........\........\....\................................\_primary.dat
...........\..........\........\....\................................\_primary.vhd
...........\..........\........\....\.m@f_pll_reg\verilog.asm
...

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