Monocycle cpu assembly line design

cod_lab6_all\alu.v
............\AluCtr.v
............\Ctr.v
............\doc\Assembler\example.asm
............\...\.........\mips.pl
............\...\.........\Mips指令集.html
............\...\.........\result.txt
............\...\.........\使用说明.txt
............\...\data.txt
............\...\example.asm
............\...\ModelSim使用说明.doc
............\...\SOME-COD-LAB-006.doc
............\...\~$ME-COD-LAB-006.doc
............\lab6\.lso
............\....\AluCtr.prj
............\....\AluCtr.stx
............\....\AluCtr.xst
............\....\compxlib.cfg
............\....\compxlib.log
............\....\data.txt
............\....\example.asm
............\....\Instruction_Memory.v
............\....\lab6.ise
............\....\lab6.ise_ISE_Backup
............\....\lab6.restore
............\....\memory.prj
............\....\memory.stx
............\....\memory.xst
............\....\model.list
............\....\modelsim.ini
............\....\result.txt
............\....\test_TOP6.ado
............\....\test_TOP6.ano
............\....\test_TOP6.ant
............\....\test_TOP6.fdo
............\....\test_TOP6.jhd
............\....\test_TOP6.tbw
............\....\test_TOP6.tfw
............\....\test_TOP6.udo
............\....\test_TOP6.xwv
............\....\test_TOP6.xwv_bak
............\....\test_TOP6_bencher.prj
............\....\TOP6.fdo
............\....\TOP6.prj
............\....\TOP6.stx
............\....\TOP6.udo
............\....\TOP6.v
............\....\TOP6.xst
............\....\transcript
............\....\vsim.wlf
............\....\wire_connenct.prj
............\....\wire_connenct.stx
............\....\wire_connenct.xst
............\....\.ork\@alu@ctr\verilog.asm
............\....\....\........\_primary.dat
............\....\....\........\_primary.vhd
............\....\....\.ctr\verilog.asm
............\....\....\....\_primary.dat
............\....\....\....\_primary.vhd
............\....\....\.instruction_@memory\verilog.asm
............\....\....\....................\_primary.dat
............\....\....\....................\_primary.vhd
............\....\....\.t@o@p6\verilog.asm
............\....\....\.......\_primary.dat
............\....\....\.......\_primary.vhd
............\....\....\alu\verilog.asm
............\....\....\...\_primary.dat
............\....\....\...\_primary.vhd
............\....\....\glbl\verilog.asm
............\....\....\....\_primary.dat
............\....\....\....\_primary.vhd
............\....\....\memory\verilog.asm
............\....\....\......\_primary.dat
............\....\....\......\_primary.vhd
............\....\....\register\verilog.asm
............\....\....\........\_primary.dat
............\....\....\........\_primary.vhd
............\....\....\signext\verilog.asm
............\....\....\.......\_primary.dat
............\....\....\.......\_primary.vhd
............\....\....\test_@t@o@p6\verilog.asm
............\....\....\............\_primary.dat
............\....\....\............\_primary.vhd
............\....\....\.....top6\testbench_arch.asm
............\....\....\.........\testbench_arch.dat
............\....\....\.........\_primary.dat
............\....\....\_info
............\....\xst\work\hdllib.ref
............\....\...\....\vlg01\_t_o_p6.bin
............\....\...\....\....3\_alu_ctr.bin
............\....\...\....\....A\alu.bin
............\....\...\....\...1A\wire__connenct.bin
............\....\...\....\....E\signext.bin
............\....\...\....\...22\_instruction___memory.bin
............\....\...\....\....9\register.bin
............\....\...\....\...41\_ctr.bin
............\....\...\....\...69\memory.bin
............\....\_xmsgs\xst.xmsgs
............\....\__ISE_repository_lab6.ise_.lock
............\lab6.bmp

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