Verilog code in the document of the FPGA data bus protocol and SSI links

FPGA-SSI\db\encoder_test_final.asm.qmsg
........\..\encoder_test_final.asm_labs.ddb
........\..\encoder_test_final.cbx.xml
........\..\encoder_test_final.cmp.bpm
........\..\encoder_test_final.cmp.cdb
........\..\encoder_test_final.cmp.ecobp
........\..\encoder_test_final.cmp.hdb
........\..\encoder_test_final.cmp.logdb
........\..\encoder_test_final.cmp.rdb
........\..\encoder_test_final.cmp.tdb
........\..\encoder_test_final.cmp0.ddb
........\..\encoder_test_final.cmp2.ddb
........\..\encoder_test_final.cmp_bb.cdb
........\..\encoder_test_final.cmp_bb.hdb
........\..\encoder_test_final.cmp_bb.logdb
........\..\encoder_test_final.cmp_bb.rcf
........\..\encoder_test_final.dbp
........\..\encoder_test_final.db_info
........\..\encoder_test_final.eco.cdb
........\..\encoder_test_final.fit.qmsg
........\..\encoder_test_final.hier_info
........\..\encoder_test_final.hif
........\..\encoder_test_final.map.bpm
........\..\encoder_test_final.map.cdb
........\..\encoder_test_final.map.ecobp
........\..\encoder_test_final.map.hdb
........\..\encoder_test_final.map.logdb
........\..\encoder_test_final.map.qmsg
........\..\encoder_test_final.map_bb.cdb
........\..\encoder_test_final.map_bb.hdb
........\..\encoder_test_final.map_bb.logdb
........\..\encoder_test_final.pre_map.cdb
........\..\encoder_test_final.pre_map.hdb
........\..\encoder_test_final.psp
........\..\encoder_test_final.pss
........\..\encoder_test_final.rtlv.hdb
........\..\encoder_test_final.rtlv_sg.cdb
........\..\encoder_test_final.rtlv_sg_swap.cdb
........\..\encoder_test_final.sgdiff.cdb
........\..\encoder_test_final.sgdiff.hdb
........\..\encoder_test_final.signalprobe.cdb
........\..\encoder_test_final.sld_design_entry.sci
........\..\encoder_test_final.sld_design_entry_dsc.sci
........\..\encoder_test_final.syn_hier_info
........\..\encoder_test_final.tan.qmsg
........\..\prev_cmp_encoder_test_final.asm.qmsg
........\..\prev_cmp_encoder_test_final.fit.qmsg
........\..\prev_cmp_encoder_test_final.map.qmsg
........\..\prev_cmp_encoder_test_final.tan.qmsg
........\DSPram1.v
........\encoder_test_final.asm.rpt
........\encoder_test_final.done
........\encoder_test_final.dpf
........\encoder_test_final.fit.rpt
........\encoder_test_final.fit.smsg
........\encoder_test_final.fit.summary
........\encoder_test_final.flow.rpt
........\encoder_test_final.map.rpt
........\encoder_test_final.map.smsg
........\encoder_test_final.map.summary
........\encoder_test_final.pin
........\encoder_test_final.pof
........\encoder_test_final.qpf
........\encoder_test_final.qsf
........\encoder_test_final.qws
........\encoder_test_final.sof
........\encoder_test_final.tan.rpt
........\encoder_test_final.tan.summary
........\fdivision_set.bsf
........\fdivision_set.v
........\fdivision_set.v.bak
........\fdivision_ssi.v
........\fdivision_unequal.v
........\gray_selector.v
........\pll.bsf
........\pll.ppf
........\pll.v
........\pll_wave0.jpg
........\pll_waveforms.html
........\prev_cmp_encoder_test_final.qmsg
........\rd_data.v
........\serial_to_parallel.v
........\ssi.bdf
........\ssi.bsf
........\ssi_8.bdf
........\ssi_clk.v
........\db
FPGA-SSI

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