This is a VHDL language with 16-bit divider, frequency effects can be achieved, is a complete code, we can participate in detailed reference.

16位分频器\db\PULSE.asm.qmsg
..........\..\PULSE.cbx.xml
..........\..\PULSE.cmp.cdb
..........\..\PULSE.cmp.hdb
..........\..\PULSE.cmp.logdb
..........\..\PULSE.cmp.qrpt
..........\..\PULSE.cmp.rdb
..........\..\PULSE.cmp.tdb
..........\..\PULSE.cmp0.ddb
..........\..\PULSE.dbp
..........\..\PULSE.db_info
..........\..\PULSE.eco.cdb
..........\..\PULSE.eds_overflow
..........\..\PULSE.fit.qmsg
..........\..\PULSE.hier_info
..........\..\PULSE.hif
..........\..\PULSE.map.cdb
..........\..\PULSE.map.hdb
..........\..\PULSE.map.logdb
..........\..\PULSE.map.qmsg
..........\..\PULSE.pre_map.cdb
..........\..\PULSE.pre_map.hdb
..........\..\PULSE.psp
..........\..\PULSE.rtlv.hdb
..........\..\PULSE.rtlv_sg.cdb
..........\..\PULSE.rtlv_sg_swap.cdb
..........\..\PULSE.sgdiff.cdb
..........\..\PULSE.sgdiff.hdb
..........\..\PULSE.signalprobe.cdb
..........\..\PULSE.sim.hdb
..........\..\PULSE.sim.qmsg
..........\..\PULSE.sim.rdb
..........\..\PULSE.sld_design_entry.sci
..........\..\PULSE.sld_design_entry_dsc.sci
..........\..\PULSE.syn_hier_info
..........\..\PULSE.tan.qmsg
..........\PULSE.asm.rpt
..........\PULSE.done
..........\PULSE.fit.eqn
..........\PULSE.fit.rpt
..........\PULSE.fit.summary
..........\PULSE.flow.rpt
..........\PULSE.map.eqn
..........\PULSE.map.rpt
..........\PULSE.map.summary
..........\PULSE.pin
..........\PULSE.pof
..........\PULSE.qpf
..........\PULSE.qsf
..........\PULSE.qws
..........\PULSE.sim.rpt
..........\PULSE.sof
..........\PULSE.tan.rpt
..........\PULSE.tan.summary
..........\PULSE.vhd
..........\PULSE.vwf
..........\db
16位分频器

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