FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this

UART
....\component
....\constraint
....\coreconsole
....\designer
....\........\impl1
....\........\.....\designer.log
....\........\.....\simulation
....\........\.....\uart_test.adb
....\........\.....\uart_test.dtf
....\........\.....\.............\verify.log
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\hdl
....\...\rec.v
....\...\send.v
....\...\uart_test.v
....\phy_synthesis
....\simulation
....\..........\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\smartgen
....\........\smartgen.aws
....\stimulus
....\synthesis
....\.........\stdout.log
....\.........\syntmp
....\.........\......\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\UART.prj
....\UART.prj.convert.7.3.bak
....\viewdraw
....\........\sch
....\........\sym
....\........\vf
....\........\..\project.lst
....\........\viewdraw.ini
....\........\wir

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