This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.

ddr_100Mhz_2011.03.12\datasheet.txt
.....................\log.txt
.....................\mig.prj
.....................\par\coregen.cgc
.....................\...\coregen.cgp
.....................\...\create_ise.bat
.....................\...\dcm1_arwz.ucf
.....................\...\dcm2_arwz.ucf
.....................\...\dcm_100M.tfi
.....................\...\dcm_100M.v
.....................\...\dcm_100M_arwz.ucf
.....................\...\ddr.ucf
.....................\...\ddr_bitgen.xwbt
.....................\...\ddr_guide.ncd
.....................\...\ddr_model.v
.....................\...\delect.v
.....................\...\delect_arwz.ucf
.....................\...\glbl.v
.....................\...\icon_coregen.xco
.....................\...\ila_coregen.xco
.....................\...\.pcore_dir\dcm1.cgc
.....................\...\..........\dcm1.v
.....................\...\..........\dcm1.xaw
.....................\...\..........\dcm1_arwz.ucf
.....................\...\..........\dcm1_flist.txt
.....................\...\..........\dcm1_xmdf.tcl
.....................\...\..........\dcm2.cgc
.....................\...\..........\dcm2.v
.....................\...\..........\dcm2.xaw
.....................\...\..........\dcm2_arwz.ucf
.....................\...\..........\dcm2_flist.txt
.....................\...\..........\dcm2_xmdf.tcl
.....................\...\..........\dcm3.cgc
.....................\...\..........\dcm3.cgp
.....................\...\..........\dcm_100M.cgc
.....................\...\..........\dcm_100M.cgp
.....................\...\..........\dcm_100M.v
.....................\...\..........\dcm_100M.xaw
.....................\...\..........\dcm_100M_arwz.ucf
.....................\...\..........\dcm_100M_flist.txt
.....................\...\..........\dcm_100M_readme.txt
.....................\...\..........\dcm_100M_xmdf.tcl
.....................\...\..........\delect.cgc
.....................\...\..........\delect.cgp
.....................\...\..........\delect.v
.....................\...\..........\delect.xaw
.....................\...\..........\delect_arwz.ucf
.....................\...\..........\delect_flist.txt
.....................\...\..........\delect_readme.txt
.....................\...\..........\delect_xmdf.tcl
.....................\...\..........\fafa.cgc
.....................\...\..........\fafa.cgp
.....................\...\..........\ila.asy
.....................\...\..........\ila.cdc
.....................\...\..........\ila.cgc
.....................\...\..........\ila.cgp
.....................\...\..........\ila.gise
.....................\...\..........\ila.ngc
.....................\...\..........\ila.v
.....................\...\..........\ila.veo
.....................\...\..........\ila.vhd
.....................\...\..........\ila.vho
.....................\...\..........\ila.xco
.....................\...\..........\ila.xise
.....................\...\..........\ila_flist.txt
.....................\...\..........\ila_readme.txt
.....................\...\..........\ila_xmdf.tcl
.....................\...\..........\xaw2verilog.log
.....................\...\..........\yui.cgc
.....................\...\..........\yui.cgp
.....................\...\..........\_xmsgs\netgen.xmsgs
.....................\...\..........\......\pn_parser.xmsgs
.....................\...\..........\......\xst.xmsgs
.....................\...\.seconfig\ddr.xreport
.....................\...\.........\test.projectmgr
.....................\...\.........\top.xreport
.....................\...\ise_flow.bat
.....................\...\ise_run.txt
.....................\...\makeproj.bat
.....................\...\mem_interface_top.ut
.....................\...\modelsim.ini
.....................\...\readme.txt
.....................\...\rem_files.bat
.....................\...\set_ise_prop.tcl
.....................\...\set_ise_prop.tcl.bak
.....................\...\sim_tb_top.udo
.....................\...\sim_tb_top.v
.....................\...\sim_tb_top_wave.fdo
.....................\...\.ystem\system.create.tcl
.....................\...\test.gise
.......

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．