To be commercial cpu 8-bit high-speed chip design, verilog language compiler, ISE platform to complete

Leg8\add8.inc
....\add8.tdf
....\add8_wave0.jpg
....\add8_waveforms.html
....\cmp_state.ini
....\DEFINE.ACF
....\DEFINE.V
....\Leg8.asm.rpt
....\Leg8.cdf
....\Leg8.done
....\Leg8.eda.rpt
....\Leg8.fit.eqn
....\Leg8.fit.rpt
....\Leg8.fit.summary
....\Leg8.fld
....\Leg8.flow.rpt
....\Leg8.map.eqn
....\Leg8.map.rpt
....\Leg8.map.summary
....\Leg8.pin
....\Leg8.pof
....\LEG8.PROG
....\Leg8.qpf
....\Leg8.qsf
....\Leg8.qws
....\Leg8.sim.rpt
....\Leg8.sof
....\Leg8.tan.rpt
....\Leg8.tan.summary
....\Leg8.v
....\Leg8bak.v
....\Leg8var.v
....\Leg8_timesim.v
....\board\ibis\leg8.ibs
....\db\altsyncram_0g31.tdf
....\..\altsyncram_3k51.tdf
....\..\Leg8.asm.qmsg
....\..\Leg8.cmp.cdb
....\..\Leg8.cmp.ddb
....\..\Leg8.cmp.hdb
....\..\Leg8.cmp.rdb
....\..\Leg8.db_info
....\..\Leg8.eco.cdb
....\..\Leg8.eda.qmsg
....\..\Leg8.fit.qmsg
....\..\Leg8.frm.hdb
....\..\Leg8.hier_info
....\..\Leg8.hif
....\..\Leg8.icc
....\..\Leg8.map.cdb
....\..\Leg8.map.hdb
....\..\Leg8.map.qmsg
....\..\Leg8.pre_map.cdb
....\..\Leg8.pre_map.hdb
....\..\Leg8.psp
....\..\Leg8.rtlv.hdb
....\..\Leg8.rtlv_sg.cdb
....\..\Leg8.rtlv_sg_swap.cdb
....\..\Leg8.sgdiff.cdb
....\..\Leg8.sgdiff.hdb
....\..\Leg8.sim.hdb
....\..\Leg8.sim.qmsg
....\..\Leg8.sim.rdb
....\..\Leg8.sld_design_entry.sci
....\..\Leg8.sld_design_entry_dsc.sci
....\..\Leg8.swb.qmsg
....\..\Leg8.syn_hier_info
....\..\Leg8.tan.qmsg
....\..\Leg8_cmp.qrpt
....\..\Leg8_sim.qrpt
....\simulation\modelsim\Leg8.vo
....\..........\........\Leg8_modelsim.xrf
....\..........\........\Leg8_v.sdo
....\timing\primetime\Leg8.vo
....\......\.........\Leg8_pt_v.tcl
....\......\.........\Leg8_v.sdo
....\board\ibis
....\simulation\modelsim
....\timing\primetime
....\board
....\db
....\simulation
....\timing
Leg8

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