This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating C code, the sdc and ucf files for the FPGA synthiese, help document.

Camera_Interface_Verilog\bench\verilog\camera_bench_defines.v
........................\.....\.......\camera_bench_top.v
........................\.....\.......\wb_master32.v
........................\.....\.......\wb_master_behavioral.v
........................\.....\.......\wb_master_defines.v
........................\.....\.......\wb_slave_behavioral.v
........................\doc\camera_specification.pdf
........................\rtl\verilog\camera_async_reset_flop.v
........................\...\.......\camera_cb_table.v
........................\...\.......\camera_cr_table.v
........................\...\.......\camera_defines.v
........................\...\.......\camera_fifo.v
........................\...\.......\camera_fifo_ctrl.v
........................\...\.......\camera_io_calc.v
........................\...\.......\camera_synchronizer_flop.v
........................\...\.......\camera_sync_ctrl.v
........................\...\.......\camera_top.v
........................\...\.......\camera_tpram.v
........................\...\.......\camera_wb_if.v
........................\...\.......\camera_y_table.v
........................\...\.......\timescale.v
........................\sim\core_sw_simulator\b_cb.dat
........................\...\.................\gen_yuv_rgb_files
........................\...\.................\gen_yuv_rgb_files.c
........................\...\.................\g_b_cb_case.dat
........................\...\.................\g_cb.dat
........................\...\.................\g_cr.dat
........................\...\.................\rgb_out.dat
........................\...\.................\rgb_scale_out.dat
........................\...\.................\rgb_y.dat
........................\...\.................\rgb_y_case.dat
........................\...\.................\r_cr.dat
........................\...\.................\r_g_cr_case.dat
........................\...\.................\uyvy_in.dat
........................\...\.................\yuv422_to_rgb
........................\...\.................\yuv422_to_rgb.c
........................\...\rtl_sim\bin\artisan_file_list.lst
........................\...\.......\...\cds.lib
........................\...\.......\...\hdl.var
........................\...\.......\...\ncelab.args
........................\...\.......\...\ncelab_xilinx.args
........................\...\.......\...\ncsim.rc
........................\...\.......\...\ncsim_waves.rc
........................\...\.......\...\rtl_file_list.lst
........................\...\.......\...\sim_file_list.lst
........................\...\.......\...\xilinx_file_list.lst
........................\...\.......\log\ncelab_xilinx.log
........................\...\.......\...\ncsim.log
........................\...\.......\...\ncvlog.log
........................\...\.......\run\clean
........................\...\.......\...\ncsim.args
........................\...\.......\...\ncsim.key
........................\...\.......\...\ncvlog.args
........................\...\.......\...\README.txt
........................\...\.......\...\run_cam_sim_regr.scr
........................\...\.......\...\top_groups.do
........................\.yn\xilinx\constraints\camera.sdc
........................\...\......\...........\camera.ucf
........................\.im\rtl_sim\bin\INCA_libs\worklib
........................\...\.......\...\INCA_libs
........................\...\.......\bin
........................\...\.......\log
........................\...\.......\out
........................\...\.......\run
........................\.yn\xilinx\constraints
........................\bench\verilog
........................\rtl\verilog
........................\sim\core_sw_simulator
........................\...\rtl_sim
........................\.yn\xilinx
........................\bench
........................\doc
........................\rtl
........................\sim
........................\syn
Camera_Interface_Verilog

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