This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language

EX4\verilogled7\db\led_seg7.db_info
...\...........\..\led_seg7.eco.cdb
...\...........\..\led_seg7.sld_design_entry.sci
...\...........\..\prev_cmp_led_seg7.asm.qmsg
...\...........\..\prev_cmp_led_seg7.fit.qmsg
...\...........\..\prev_cmp_led_seg7.map.qmsg
...\...........\..\prev_cmp_led_seg7.qmsg
...\...........\..\prev_cmp_led_seg7.tan.qmsg
...\...........\incremental_db\compiled_partitions\led_seg7.root_partition.map.kpt
...\...........\..............\README
...\...........\led_seg7.asm.rpt
...\...........\led_seg7.cdf
...\...........\led_seg7.done
...\...........\led_seg7.dpf
...\...........\led_seg7.fit.rpt
...\...........\led_seg7.fit.smsg
...\...........\led_seg7.fit.summary
...\...........\led_seg7.flow.rpt
...\...........\led_seg7.map.rpt
...\...........\led_seg7.map.summary
...\...........\led_seg7.pin
...\...........\led_seg7.pof
...\...........\led_seg7.qpf
...\...........\led_seg7.qsf
...\...........\led_seg7.qws
...\...........\led_seg7.tan.rpt
...\...........\led_seg7.tan.summary
...\...........\led_seg7.v
...\...........\led_seg7.v.bak
...\...........\led_seg7_assignment_defaults.qdf
...\...........\transcript
...\...........\incremental_db\compiled_partitions
...\...........\db
...\...........\incremental_db
...\verilogled7
EX4

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