VGA-based fpga code has been tested successfully

DE0_VGA\.sopc_builder\filters.xml
.......\db\DE0_VGA.asm.qmsg
.......\..\DE0_VGA.asm.rdb
.......\..\DE0_VGA.asm_labs.ddb
.......\..\DE0_VGA.cbx.xml
.......\..\DE0_VGA.cmp.bpm
.......\..\DE0_VGA.cmp.cbp
.......\..\DE0_VGA.cmp.cdb
.......\..\DE0_VGA.cmp.ecobp
.......\..\DE0_VGA.cmp.hdb
.......\..\DE0_VGA.cmp.kpt
.......\..\DE0_VGA.cmp.logdb
.......\..\DE0_VGA.cmp.rdb
.......\..\DE0_VGA.cmp_merge.kpt
.......\..\DE0_VGA.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
.......\..\DE0_VGA.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
.......\..\DE0_VGA.db_info
.......\..\DE0_VGA.eco.cdb
.......\..\DE0_VGA.fit.qmsg
.......\..\DE0_VGA.hier_info
.......\..\DE0_VGA.hif
.......\..\DE0_VGA.lpc.html
.......\..\DE0_VGA.lpc.rdb
.......\..\DE0_VGA.lpc.txt
.......\..\DE0_VGA.map.bpm
.......\..\DE0_VGA.map.cdb
.......\..\DE0_VGA.map.ecobp
.......\..\DE0_VGA.map.hdb
.......\..\DE0_VGA.map.kpt
.......\..\DE0_VGA.map.logdb
.......\..\DE0_VGA.map.qmsg
.......\..\DE0_VGA.map_bb.cdb
.......\..\DE0_VGA.map_bb.hdb
.......\..\DE0_VGA.map_bb.logdb
.......\..\DE0_VGA.pre_map.cdb
.......\..\DE0_VGA.pre_map.hdb
.......\..\DE0_VGA.rpp.qmsg
.......\..\DE0_VGA.rtlv.hdb
.......\..\DE0_VGA.rtlv_sg.cdb
.......\..\DE0_VGA.rtlv_sg_swap.cdb
.......\..\DE0_VGA.sgate.rvd
.......\..\DE0_VGA.sgate_sm.rvd
.......\..\DE0_VGA.sgdiff.cdb
.......\..\DE0_VGA.sgdiff.hdb
.......\..\DE0_VGA.sld_design_entry.sci
.......\..\DE0_VGA.sld_design_entry_dsc.sci
.......\..\DE0_VGA.smart_action.txt
.......\..\DE0_VGA.sta.qmsg
.......\..\DE0_VGA.sta.rdb
.......\..\DE0_VGA.sta_cmp.6_slow_1200mv_85c.tdb
.......\..\DE0_VGA.syn_hier_info
.......\..\DE0_VGA.tiscmp.fast_1200mv_0c.ddb
.......\..\DE0_VGA.tiscmp.slow_1200mv_0c.ddb
.......\..\DE0_VGA.tiscmp.slow_1200mv_85c.ddb
.......\..\DE0_VGA.tis_db_list.ddb
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_DE0_VGA.asm.qmsg
.......\..\prev_cmp_DE0_VGA.fit.qmsg
.......\..\prev_cmp_DE0_VGA.map.qmsg
.......\..\prev_cmp_DE0_VGA.sta.qmsg
.......\..\VGA_CLK_altpll.v
.......\DE0_VGA.asm.rpt
.......\DE0_VGA.done
.......\DE0_VGA.fit.rpt
.......\DE0_VGA.fit.smsg
.......\DE0_VGA.fit.summary
.......\DE0_VGA.flow.rpt
.......\DE0_VGA.map.rpt
.......\DE0_VGA.map.summary
.......\DE0_VGA.pin
.......\DE0_VGA.qpf
.......\DE0_VGA.qsf
.......\DE0_VGA.qws
.......\DE0_VGA.sof
.......\DE0_VGA.sta.rpt
.......\DE0_VGA.sta.summary
.......\DE0_VGA.v
.......\DE0_VGA_assignment_defaults.qdf
.......\incremental_db\compiled_partitions\DE0_VGA.root_partition.cmp.atm
.......\..............\...................\DE0_VGA.root_partition.cmp.cdb
.......\..............\...................\DE0_VGA.root_partition.cmp.dfp
.......\..............\...................\DE0_VGA.root_partition.cmp.hdb
.......\..............\...................\DE0_VGA.root_partition.cmp.hdbx
.......\..............\...................\DE0_VGA.root_partition.cmp.kpt
.......\..............\...................\DE0_VGA.root_partition.cmp.logdb
.......\..............\...................\DE0_VGA.root_partition.cmp.rcf
.......\..............\...................\DE0_VGA.root_partition.cmp.rcfdb
.......\..............\...................\DE0_VGA.root_partition.cmp.re.rcfdb
.......\..............\...................\DE0_VGA.root_partition.map.atm
.......\..............\...................\DE0_VGA.root_partition.map.cdb
.......\..............\...................\DE0_VGA.root_partition.map.dpi
.......\..............\...................\DE0_VGA.root_partition.map.hdb
.......\..............\...................\DE0_VGA.root_partition.map.hdbx
.......\..............\...................\DE0_VGA.root_partition.map.kpt
.......\..............\...................\DE0_VGA.root_partition.merge_hb.atm
.......\..............\README
.......\PLLJ_PLLSPE_INFO.txt
.......\sopc_builder_log.txt
.......\V\VGA_CLK.v
.......\.\VGA_Ctrl.v

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