CIC filter a very good program!

cic\auk_dspip_avalon_streaming_controller.vhd
...\auk_dspip_avalon_streaming_sink.vhd
...\auk_dspip_avalon_streaming_source.vhd
...\auk_dspip_delay.vhd
...\auk_dspip_fastadd.vhd
...\auk_dspip_fastaddsub.vhd
...\auk_dspip_lib_pkg.vhd
...\auk_dspip_math_pkg.vhd
...\auk_dspip_roundsat.vhd
...\cic.asm.rpt
...\cic.done
...\cic.eda.rpt
...\cic.fit.eqn
...\cic.fit.rpt
...\cic.fit.summary
...\cic.flow.rpt
...\cic.map.eqn
...\cic.map.rpt
...\cic.map.summary
...\cic.pin
...\cic.pof
...\cic.qpf
...\cic.qsf
...\cic.qws
...\cic.sof
...\cic.tan.rpt
...\cic.tan.summary
...\cic.vhd
...\cic_test_tb.v
...\cic_test_tb.v.bak
...\cic_test_tb_input.txt
...\cic_test_tb_output.txt
...\db\cic.analyze_file.qmsg
...\..\cic.asm.qmsg
...\..\cic.cbx.xml
...\..\cic.cmp.cdb
...\..\cic.cmp.hdb
...\..\cic.cmp.qrpt
...\..\cic.cmp.rdb
...\..\cic.cmp.tdb
...\..\cic.cmp0.ddb
...\..\cic.dbp
...\..\cic.db_info
...\..\cic.eco.cdb
...\..\cic.eda.qmsg
...\..\cic.fit.qmsg
...\..\cic.hier_info
...\..\cic.hif
...\..\cic.map.cdb
...\..\cic.map.hdb
...\..\cic.map.qmsg
...\..\cic.pre_map.cdb
...\..\cic.pre_map.hdb
...\..\cic.psp
...\..\cic.rtlv.hdb
...\..\cic.rtlv_sg.cdb
...\..\cic.rtlv_sg_swap.cdb
...\..\cic.sgdiff.cdb
...\..\cic.sgdiff.hdb
...\..\cic.signalprobe.cdb
...\..\cic.sld_design_entry.sci
...\..\cic.sld_design_entry_dsc.sci
...\..\cic.syn_hier_info
...\..\cic.tan.qmsg
...\db
...\fdf.bsf
...\fdf.cmp
...\fdf.html
...\fdf.log
...\fdf.vhd
...\fdf_cic.ocp
...\fdf_cic.vhd
...\fdf_nativelink.tcl
...\fdf_quartus.tcl
...\fdf_tb.vhd
...\fdf_tb_input.txt
...\jifen.vhd
...\quartus_nativelink_simulation.log
...\simulation\modelsim\cic.vho
...\..........\........\cic_modelsim.xrf
...\..........\........\cic_run_msim_gate_vhdl.do
...\..........\........\cic_run_msim_gate_vhdl.do.bak
...\..........\........\cic_run_msim_gate_vhdl.do.bak1
...\..........\........\cic_run_msim_gate_vhdl.do.bak2
...\..........\........\cic_run_msim_gate_vhdl.do.bak3
...\..........\........\cic_run_msim_gate_vhdl.do.bak4
...\..........\........\cic_run_msim_gate_vhdl.do.bak5
...\..........\........\cic_run_msim_gate_vhdl.do.bak6
...\..........\........\cic_run_msim_gate_vhdl.do.bak7
...\..........\........\cic_test_tb_output.txt
...\..........\........\cic_vhd.sdo
...\..........\........\fdf_tb_input.txt
...\..........\........\gate_work\cic\structure.asm
...\..........\........\.........\...\structure.dat
...\..........\........\.........\...\_primary.dat
...\..........\........\.........\cic
...\..........\........\.........\..._test_tb\verilog.asm
...\..........\........\.........\...........\_primary.dat
...\..........\........\.........\...........\_primary.vhd
...\..........\........\.........\cic_test_tb

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