ADSP2100 the Verilog source code can be integrated. ADSP2100 is used in a wide range of 3, one of DSP architecture, it is less popular, but its structure rather elaborate, and now the processor styles, friends who are interested can look at.

ADSP2100\src\x_def.v
........\...\BDMA\m_bdma.v
........\...\....\m_bdma_dummy.v
........\...\....\CVS\Entries
........\...\....\...\Repository
........\...\....\...\Root
........\...\....\CVS
........\...\BDMA
........\...\.TB\c_btb.v
........\...\...\c_btb_dummy.v
........\...\...\m_btbmemx.v
........\...\...\m_rtbmemx.v
........\...\...\reg
........\...\...\CVS\Entries
........\...\...\...\Repository
........\...\...\...\Root
........\...\...\CVS
........\...\BTB
........\...\CODEC\FXADDA162H90A\ADC162H90A_dtop.v
........\...\.....\.............\ADDA162H90A_atop.v
........\...\.....\.............\ADDA162H90A_atop.v.src
........\...\.....\.............\DAC162H90A_dtop.v
........\...\.....\.............\dac_48k_16b_1875_0db.in
........\...\.....\.............\dac_48k_16b_937_0db.in
........\...\.....\.............\decode.v
........\...\.....\.............\fir_8x.v
........\...\.....\.............\FS90B779.v
........\...\.....\.............\FS90B779_DAI.v
........\...\.....\.............\FS90B779_DAI_loop.v
........\...\.....\.............\FS90B779_sim.v
........\...\.....\.............\FXADDA162H90A.v
........\...\.....\.............\FXADDA162H90A.v.src
........\...\.....\.............\FXADDA162H90A_syn.v
........\...\.....\.............\header.v
........\...\.....\.............\MCLK_Delay.v
........\...\.....\.............\ram_32_44.v
........\...\.....\.............\run2
........\...\.....\.............\CVS\Entries
........\...\.....\.............\...\Repository
........\...\.....\.............\...\Root
........\...\.....\.............\CVS
........\...\.....\FXADDA162H90A
........\...\.....\CVS\Entries
........\...\.....\...\Repository
........\...\.....\...\Root
........\...\.....\CVS
........\...\CODEC
........\...\DAG\d_adder15.v
........\...\...\d_cla15.v
........\...\...\d_csa15.v
........\...\...\d_csa_d.v
........\...\...\d_dag.v
........\...\...\d_ILM1reg.v
........\...\...\d_ILM2reg.v
........\...\...\d_lpn.v
........\...\...\d_moduloL1.v
........\...\...\d_moduloL2.v
........\...\DAG
........\...\.EC\c_dec.v
........\...\DEC
........\...\.FT\wrapper.v
........\...\DFT
........\...\EU\SHT\es_array.v
........\...\..\...\es_dec.v
........\...\..\...\es_exp.v
........\...\..\...\es_reg.v
........\...\..\...\es_sht.v
........\...\..\SHT
........\...\..\MAC\em_adder.v
........\...\..\...\em_array.v
........\...\..\...\em_core.v
........\...\..\...\em_dec.v
........\...\..\...\em_mac.v
........\...\..\...\em_mvovf.v
........\...\..\...\em_part.v
........\...\..\...\em_psel_part.v
........\...\..\...\em_reg.v
........\...\..\MAC
........\...\..\CUN\ec_cun.v
........\...\..\CUN
........\...\..\ALU\ea_alu.v
........\...\..\...\ea_core.v
........\...\..\...\ea_dec.v
........\...\..\...\ea_reg.v
........\...\..\...\e_eu.v
........\...\..\ALU
........\...\EU
........\...\ICE\i_sice.v
........\...\...\i_sice_dummy.v
........\...\...\x_parser.v
........\...\...\x_parsm.v
........\...\ICE
........\...\.DMA\m_idma.v
........\...\....\m_idma_dummy.v
........\...\IDMA
........\...\LIB\idebn.v
........\...\...\m_cm4k.v
........\...\...\m_cm8k.v
........\...\...\m_dm8k.v
........\...\...\m_ecm32kx24.v

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