Red Hurricane uart procedure, I bought the course of the development board' s website

S5_UART\Doc\sscom.ini
.......\...\sscom32.exe
.......\...\UART控制器设计说明.doc
.......\...\xapp341.pdf
.......\func_sim\rcvr.v
.......\........\transcript
.......\........\txmit.v
.......\........\txmit_tf.do
.......\........\uart.cr.mti
.......\........\uart.mpf
.......\........\uart.v
.......\........\uart_if.v
.......\........\uart_tb.do
.......\........\uart_tb.v
.......\........\uart_tb_fixed.do
.......\........\vish_stacktrace.vstf
.......\........\vsim.wlf
.......\........\wave.do
.......\........\.ork\@u@a@r@t_tb\verilog.asm
.......\........\....\...........\_primary.dat
.......\........\....\...........\_primary.vhd
.......\........\....\rcvr\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\txmit\verilog.asm
.......\........\....\.....\_primary.dat
.......\........\....\.....\_primary.vhd
.......\........\....\uart\verilog.asm
.......\........\....\....\_primary.dat
.......\........\....\....\_primary.vhd
.......\........\....\...._if\verilog.asm
.......\........\....\.......\_primary.dat
.......\........\....\.......\_primary.vhd
.......\........\....\_info
.......\physical\altclklock0.bsf
.......\........\altclklock0.v
.......\........\altclklock0_bb.v
.......\........\async_transmitter.bsf
.......\........\cmp_state.ini
.......\........\div.bsf
.......\........\div_2.bsf
.......\........\div_2.v
.......\........\filter.bsf
.......\........\LED_flush.bsf
.......\........\rcvr.bsf
.......\........\simulation\modelsim\cyclone_atoms.v
.......\........\..........\........\uart_if.vo
.......\........\..........\........\uart_if_modelsim.xrf
.......\........\..........\........\uart_if_v.sdo
.......\........\..........\........\uart_post.cr.mti
.......\........\..........\........\uart_post.mpf
.......\........\..........\........\work\@p@r@i@m_@d@f@f@e\verilog.asm
.......\........\..........\........\....\.................\_primary.dat
.......\........\..........\........\....\.................\_primary.vhd
.......\........\..........\........\....\.u@a@r@t_tb\verilog.asm
.......\........\..........\........\....\...........\_primary.dat
.......\........\..........\........\....\...........\_primary.vhd
.......\........\..........\........\....\and1\verilog.asm
.......\........\..........\........\....\....\_primary.dat
.......\........\..........\........\....\....\_primary.vhd
.......\........\..........\........\....\....6\verilog.asm
.......\........\..........\........\....\.....\_primary.dat
.......\........\..........\........\....\.....\_primary.vhd
.......\........\..........\........\....\b17mux21\verilog.asm
.......\........\..........\........\....\........\_primary.dat
.......\........\..........\........\....\........\_primary.vhd
.......\........\..........\........\....\.5mux21\verilog.asm
.......\........\..........\........\....\.......\_primary.dat
.......\........\..........\........\....\.......\_primary.vhd
.......\........\..........\........\....\.mux21\verilog.asm
.......\........\..........\........\....\......\_primary.dat
.......\........\..........\........\....\......\_primary.vhd
.......\........\..........\........\....\cyclone_asmiblock\verilog.asm
.......\........\..........\........\....\.................\_primary.dat
.......\........\..........\........\....\.................\_primary.vhd
.......\........\..........\........\....\..........ynch_io\verilog.asm
.......\........\..........\........\....\.................\_primary.dat
.......\........\..........\........\....\.................\_primary.vhd
.......\........\..........\........\....\...............lcell\verilog.asm
.......\........\..........\........\....\....................\_primary.dat
.......\........\..........\........\....\....................\_primary.vhd
.......\........\..........\........\....\........crcblock\verilog.asm
.......\........\..........\........\....\................\_primary.dat
.......\........\..........\........\....\................\_primary.vhd
.......\........\..........\........\....\........dll\verilog.asm
.......\.....

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