DS1WM master for controlling one wire devices like DS18B20

delivery
........\design
........\......\verilog_src
........\......\...........\ds1wm
........\......\...........\.....\clk_prescaler.v
........\......\...........\.....\ds1wm.v
........\......\...........\.....\onewiremaster.v
........\......\...........\.....\one_wire_interface.v
........\......\...........\.....\one_wire_io.v
........\......\vhdl_src
........\......\........\ds1wm
........\......\........\.....\clk_prescaler.vhd
........\......\........\.....\ds1wm.vhd
........\......\........\.....\onewiremaster.vhd
........\......\........\.....\one_wire_interface.vhd
........\......\........\.....\one_wire_io.vhd
........\doc
........\...\DS1WM_Datasheet.pdf
........\...\release_notes.pdf
........\README
........\verification
........\............\verilog_src
........\............\...........\testbench
........\............\...........\.........\clkgen
........\............\...........\.........\......\clkgen.v
........\............\...........\.........\cpu_bfm
........\............\...........\.........\.......\cpu_bfm.v
........\............\...........\.........\ow_slave
........\............\...........\.........\........\cmd_ctrl.v
........\............\...........\.........\........\iox.v
........\............\...........\.........\........\ow_slave.v
........\............\...........\.........\scoreboard
........\............\...........\.........\..........\scoreboard.v
........\............\...........\.........\tb_ds1wm
........\............\...........\.........\........\tb_ds1wm.v
........\............\...........\.........\........\tc_ds1wm.v
........\............\...........\tests
........\............\...........\.....\cmd_recognition
........\............\...........\.....\...............\nc_rundir
........\............\...........\.....\...............\.........\cds.lib
........\............\...........\.....\...............\.........\design_verilog_src_files.lst
........\............\...........\.....\...............\.........\design_vhdl_src_files.lst
........\............\...........\.....\...............\.........\hdl.var
........\............\...........\.....\...............\.........\ncsim.key
........\............\...........\.....\...............\.........\probe.tcl
........\............\...........\.....\...............\.........\run.csh
........\............\...........\.....\...............\.........\tb_src_files.lst
........\............\...........\.....\...............\README
........\............\...........\.....\...............\stimulus.inc
........\............\...........\.....\multi_ow_network
........\............\...........\.....\................\nc_rundir
........\............\...........\.....\................\.........\cds.lib
........\............\...........\.....\................\.........\design_verilog_src_files.lst
........\............\...........\.....\................\.........\design_vhdl_src_files.lst
........\............\...........\.....\................\.........\hdl.var
........\............\...........\.....\................\.........\ncsim.key
........\............\...........\.....\................\.........\probe.tcl
........\............\...........\.....\................\.........\run.csh
........\............\...........\.....\................\.........\tb_src_files.lst
........\............\...........\.....\................\README
........\............\...........\.....\................\stimulus.inc
........\............\...........\.....\scratchpad_integrity
........\............\...........\.....\....................\nc_rundir
........\............\...........\.....\....................\.........\cds.lib
........\............\...........\.....\....................\.........\design_verilog_src_files.lst
........\............\...........\.....\....................\.........\design_vhdl_src_files.lst
........\............\...........\.....\....................\.........\hdl.var
........\............\...........\.....\....................\.........\ncsim.key
........\............\...........\.....\....................\.........\probe.tcl
........\

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