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100jinzhijishuqi

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 69kb
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  • Author :袁***
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Introduction - If you have any usage issues, please Google them yourself
1) counter clock input signal for the 1S (2) function of the counter counts from 0 to 99, shown in decimal form (3) has a reset terminal and the two control terminal clr plus and minus, in the role of these control signals , the counter has reset, increase or decrease of count pause function.
Packet file list
(Preview for download)
100进制计数器\biaojueqi.acf
.............\biaojueqi.hif
.............\counter100.acf
.............\counter100.fit
.............\counter100.hex
.............\counter100.hif
.............\COUNTER100.inc
.............\counter100.mmf
.............\counter100.ndb
.............\counter100.pin
.............\counter100.pof
.............\counter100.rpt
.............\counter100.scf
.............\counter100.snf
.............\counter100.sof
.............\COUNTER100.sym
.............\counter100.ttf
.............\counter100.vhd
.............\encoder.acf
.............\encoder.hif
.............\encoder.scf
.............\LIB.DLS
.............\U2989943.DLS
.............\U6950644.DLS
.............\U8156099.DLS
100进制计数器
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