altera kit gx4 on the use of DDR3 controller

ddr3_bts_GUI_C2ES_sp1\alt_mem_phy_defines.v
.....................\altera
.....................\......\90
.....................\......\..\ip
.....................\......\..\..\altera
.....................\......\..\..\......\primitives
.....................\......\..\..\......\..........\altera_avalon_st_clock_crosser
.....................\......\..\..\......\..........\..............................\altera_avalon_st_clock_crosser.v
.....................\......\..\..\......\..........\altera_avalon_st_pipeline_stage
.....................\......\..\..\......\..........\...............................\altera_avalon_st_pipeline_stage.v
.....................\......\..\..\......\sopc_builder_ip
.....................\......\..\..\......\...............\altera_avalon_jtag_phy
.....................\......\..\..\......\...............\......................\altera_avalon_st_jtag_interface.v
.....................\......\..\..\......\...............\......................\altera_jtag_dc_streaming.v
.....................\......\..\..\......\...............\......................\altera_jtag_phy.v
.....................\......\..\..\......\...............\......................\altera_jtag_streaming.v
.....................\......\..\..\......\...............\......................\altera_pli_streaming.v
.....................\......\..\..\......\...............\altera_avalon_packets_to_master
.....................\......\..\..\......\...............\...............................\altera_avalon_packets_to_master.v
.....................\......\..\..\......\...............\altera_avalon_sc_fifo
.....................\......\..\..\......\...............\.....................\altera_avalon_sc_fifo.v
.....................\......\..\..\......\...............\altera_avalon_st_bytes_to_packets
.....................\......\..\..\......\...............\.................................\altera_avalon_st_bytes_to_packets.v
.....................\......\..\..\......\...............\altera_avalon_st_idle_inserter
.....................\......\..\..\......\...............\..............................\altera_avalon_st_idle_inserter.v
.....................\......\..\..\......\...............\altera_avalon_st_idle_remover
.....................\......\..\..\......\...............\.............................\altera_avalon_st_idle_remover.v
.....................\......\..\..\......\...............\altera_avalon_st_packets_to_bytes
.....................\......\..\..\......\...............\.................................\altera_avalon_st_packets_to_bytes.v
.....................\......\..\..\......\...............\altera_jtag_avalon_master
.....................\......\..\..\......\...............\.........................\altera_jtag_avalon_master.v
.....................\......\..\..\......\...............\.........................\altera_jtag_avalon_master_common_modules.v
.....................\......\..\..\......\...............\.........................\altera_jtag_avalon_master_hw.tcl
.....................\......\..\..\......\...............\.........................\altera_jtag_avalon_master_pli_off.v
.....................\......\..\..\......\...............\.........................\altera_jtag_avalon_master_pli_on.v
.....................\altmemphy-library
.....................\.................\auk_ddr3_hp_controller.ocp
.....................\altpllpll_0.bsf
.....................\altpllpll_0.ppf
.....................\altpllpll_0.qip
.....................\altpllpll_0.v
.....................\altpllpll_0_bb.v
.....................\assignment_defaults.qdf
.....................\auk_ddr3_hp_controller.ocp
.....................\auk_ddr3_hp_controller.vhd
.....................\Copy of ddr3_bot.out.sdc
.....................\cpu_0.sdc
.....................\cpu_0.v
.....................\cpu_0_bht_ram.mif
.....................\cpu_0_dc_tag_ram.mif
.....................\cpu_0_ic_tag_ram.mif
.....................\cpu_0_jtag_debug_module_sysclk.v
.....................\cpu_0_jtag_debug_module_tck.v
.....................\cpu_0_jtag_debug_module_wrapper.v
............

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