VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system

yt7132_clock\incremental_db\compiled_partitions\yt7132_clock.root_partition.cmp.atm
............\..............\...................\yt7132_clock.root_partition.cmp.dfp
............\..............\...................\yt7132_clock.root_partition.cmp.hdbx
............\..............\...................\yt7132_clock.root_partition.cmp.kpt
............\..............\...................\yt7132_clock.root_partition.cmp.logdb
............\..............\...................\yt7132_clock.root_partition.cmp.rcf
............\..............\...................\yt7132_clock.root_partition.map.atm
............\..............\...................\yt7132_clock.root_partition.map.hdbx
............\..............\...................\yt7132_clock.root_partition.map.kpt
............\..............\...................\yt7132_clock.root_partition.map.dpi
............\..............\README
............\db\prev_cmp_yt7132_clock.qmsg
............\..\yt7132_clock.map.qmsg
............\..\prev_cmp_yt7132_clock.map.qmsg
............\..\yt7132_clock.pre_map.cdb
............\..\yt7132_clock.pre_map.hdb
............\..\yt7132_clock.lpc.txt
............\..\yt7132_clock.rtlv_sg.cdb
............\..\yt7132_clock.lpc.html
............\..\yt7132_clock.sgdiff.cdb
............\..\yt7132_clock.sgdiff.hdb
............\..\yt7132_clock.sim.cvwf
............\..\yt7132_clock.sim.hdb
............\..\yt7132_clock.sim.qmsg
............\..\yt7132_clock.sim.rdb
............\..\yt7132_clock.lpc.rdb
............\..\yt7132_clock.sld_design_entry_dsc.sci
............\..\yt7132_clock.sta.qmsg
............\..\yt7132_clock.sta.rdb
............\..\yt7132_clock.eco.cdb
............\..\yt7132_clock.syn_hier_info
............\..\yt7132_clock.tiscmp.fastest_slow_1200mv_0c.ddb
............\..\yt7132_clock.tiscmp.fastest_slow_1200mv_85c.ddb
............\..\yt7132_clock.tiscmp.fast_1200mv_0c.ddb
............\..\yt7132_clock.tiscmp.slow_1200mv_0c.ddb
............\..\yt7132_clock.tiscmp.slow_1200mv_85c.ddb
............\..\yt7132_clock.sld_design_entry.sci
............\..\yt7132_clock_global_asgn_op.abo
............\..\yt7132_clock.tmw_info
............\..\yt7132_clock.rtlv.hdb
............\..\prev_cmp_yt7132_clock.fit.qmsg
............\..\prev_cmp_yt7132_clock.asm.qmsg
............\..\prev_cmp_yt7132_clock.sta.qmsg
............\..\yt7132_clock.map_bb.hdb
............\..\yt7132_clock.map_bb.logdb
............\..\yt7132_clock.fit.qmsg
............\..\yt7132_clock.cmp.logdb
............\..\yt7132_clock.rtlv_sg_swap.cdb
............\..\yt7132_clock.map.cdb
............\..\yt7132_clock.map_bb.cdb
............\..\yt7132_clock.map.hdb
............\..\yt7132_clock.map.logdb
............\..\yt7132_clock.map.bpm
............\..\yt7132_clock.cmp.rdb
............\..\yt7132_clock.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
............\..\yt7132_clock.tis_db_list.ddb
............\..\prev_cmp_yt7132_clock.sim.qmsg
............\..\wed.wsf
............\..\yt7132_clock.asm.qmsg
............\..\yt7132_clock.cbx.xml
............\..\yt7132_clock.cmp.ecobp
............\..\yt7132_clock.cmp.kpt
............\..\yt7132_clock.cmp_merge.kpt
............\..\yt7132_clock.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
............\..\yt7132_clock.db_info
............\..\yt7132_clock.eds_overflow
............\..\yt7132_clock.hier_info
............\..\yt7132_clock.hif
............\..\yt7132_clock.map.ecobp
............\..\yt7132_clock.map.kpt
............\yt7132_baoshi.bsf
............\yt7132_baoshi.vhd
............\yt7132_baoshi.vhd.bak
............\yt7132_choice2.bsf
............\yt7132_choice2.vhd
............\yt7132_choice2.vhd.bak
............\yt7132_choice2.vwf
............\yt7132_clock.asm.rpt
............\yt7132_clock.bdf
............\yt7132_clock.done
............\yt7132_clock.dpf
............\yt7132_clock.fit.rpt
............\yt7132_clock.fit.smsg
............\yt7132_clock.fit.summary
............\yt7132_clock.map.summary
............\yt7132_clock.pin
............\yt7132_clock.qpf
............\yt7132_clock.qsf
............\yt7132_clock.sim.rpt
............\yt7132_clock.sof
............\yt7132_clock.sta.rpt
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