Wireless communication FPGA design [TianYun, etal] [source code] _2010112514154616, use Xilinx development, call modelsim simulation.

无线通信FPGA设计[田耘等编著][程序源代码] - 副本\Verilog代码\c10\10-2\mult.xco
...............................................\...........\...\....\mydds.xco
...............................................\...........\...\....\square_syn.v
...............................................\...........\...\...4\coastas_dds.v
...............................................\...........\...\....\costas_lf.v
...............................................\...........\...\....\costas_loop.v
...............................................\...........\...\....\costas_lpf.v
...............................................\...........\...\....\costas_mult.v
...............................................\...........\...\....\err_mult.v
...............................................\...........\...\....\fir_lpf.xco
...............................................\...........\...\....\mult.xco
...............................................\...........\...\....\my_dds.xco
...............................................\...........\...\...6\dearly_sub.v
...............................................\...........\...\....\dedds.v
...............................................\...........\...\....\delay_early_gate.v
...............................................\...........\...\....\de_mult.xco
...............................................\...........\...\....\eddds.xco
...............................................\...........\...\....\iir.v
...............................................\...........\...\....\iir1.v
...............................................\...........\...\...8\baker.v
...............................................\...........\..1\11-10\div16.xco
...............................................\...........\...\.....\fir_rls.v
...............................................\...........\...\.....\rlsmult.xco
...............................................\...........\...\.....\shiftreg25.xco
...............................................\...........\...\.....\shiftreg28.xco
...............................................\...........\...\.....\shiftreg3.xco
...............................................\...........\...\....2\dfe_filter.v
...............................................\...........\...\.....\dfe_mult.xco
...............................................\...........\...\....4\aa_adder.xco
...............................................\...........\...\.....\aa_bram.xco
...............................................\...........\...\.....\aa_cmult.xco
...............................................\...........\...\.....\ad_a.v
...............................................\...........\...\.....\shift16.xco
...............................................\...........\...\...2\fir_lms.v
...............................................\...........\...\...3\fir_pipline_lms.v
...............................................\...........\...\....\lmsmult.xco
...............................................\...........\...\...5\mult.xco
...............................................\...........\...\....\shiftreg4.xco
...............................................\...........\...\....\sign_fir_lms.v
...............................................\...........\...\...8\blockconnect.v
...............................................\...........\...\....\cmult.v
...............................................\...........\...\....\coe_updata.v
...............................................\...........\...\....\complex_mult.xco
...............................................\...........\...\....\fft_block.v
...............................................\...........\...\....\fft_block_lms.v
...............................................\...........\...\....\fft_w16_p32.xco
...............................................\...........\...\....\gonge.v
...............................................\...........\...\....\ifft_block.v
...............................................\...........\...\....\insert.v
...............................................\...........\...\....\save_sub.v
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