DDS which was write by Verilog。

DDS
...\add_12.v
...\clk_div.v
...\DA_control.v
...\db
...\..\add_sub_1rh.tdf
...\..\add_sub_t8i.tdf
...\..\add_sub_voh.tdf
...\..\altsyncram_7r03.tdf
...\..\altsyncram_bmi2.tdf
...\..\altsyncram_bq03.tdf
...\..\altsyncram_c331.tdf
...\..\altsyncram_hmi2.tdf
...\..\altsyncram_imi2.tdf
...\..\altsyncram_tmi2.tdf
...\..\altsyncram_ve11.tdf
...\..\altsyncram_vmi2.tdf
...\..\cmpr_fnh.tdf
...\..\cmpr_gnh.tdf
...\..\cntr_5af.tdf
...\..\cntr_daf.tdf
...\..\cntr_dhe.tdf
...\..\cntr_dkf.tdf
...\..\cntr_ebg.tdf
...\..\cntr_ekf.tdf
...\..\cntr_fbg.tdf
...\..\cntr_fgh.tdf
...\..\cntr_ghe.tdf
...\..\cntr_hhe.tdf
...\..\cntr_ngh.tdf
...\..\cntr_nhe.tdf
...\..\DDS.db_info
...\..\DDS.eco.cdb
...\..\DDS.sim_ori.vwf
...\..\DDS.sld_design_entry.sci
...\..\decode_fga.tdf
...\..\decode_iga.tdf
...\..\decode_ogi.tdf
...\..\mux_gcb.tdf
...\..\mux_pcb.tdf
...\..\wed.zsf
...\DDS.asm.rpt
...\DDS.cdf
...\DDS.done
...\DDS.dpf
...\DDS.eda.rpt
...\DDS.fit.rpt
...\DDS.fit.smsg
...\DDS.fit.summary
...\DDS.flow.rpt
...\DDS.map.rpt
...\DDS.map.summary
...\DDS.pin
...\DDS.pof
...\DDS.qpf
...\DDS.qsf
...\DDS.qws
...\DDS.sim.rpt
...\DDS.sof
...\DDS.tan.rpt
...\DDS.tan.summary
...\DDS.v
...\DDS.vwf
...\DDS_assignment_defaults.qdf
...\DSP_Interface.v
...\ff.v
...\ff_bb.v
...\fifo.v
...\fifo_bb.v
...\FreFindTable.v
...\MissileTraining.v
...\PhaseFindTable.v
...\PLL.v
...\PLL_bb.v
...\rom1.v
...\simulation
...\..........\activehdl
...\..........\.........\DDS.vo
...\..........\.........\DDS_v.sdo
...\SinFindTable.v
...\Sin_12b.mif
...\stp1.stp
...\timing
...\......\primetime
...\......\.........\DDS.vo
...\......\.........\DDS_pt_v.tcl
...\......\.........\DDS_v.sdo
...\top.v

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