This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.

High+Speed+FIFOs+In+Spartan-II+FPGAs.pdf

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