entity adderN is generic(N : integer := 16) port (a : in std_logic_vector(N downto 1) b : in std_logic_vector(N downto 1) cin : in std_logic sum : out std_logic_vector(N downto 1) cout : out std_logic) end adderN

5vadderN\adderN.asm.rpt
........\adderN.tan.summary
........\adderN.tan.rpt
........\adderN.vwf
........\adderN.sim.rpt
........\adderN.qws
........\adderN.qpf
........\adderN.qsf
........\db\adderN.db_info
........\..\adderN.cmp.tdb
........\..\adderN.sim.qmsg
........\..\adderN.map.qmsg
........\..\adderN.tan.qmsg
........\..\adderN.cbx.xml
........\..\adderN.hif
........\..\adderN.hier_info
........\..\adderN.rtlv_sg.cdb
........\..\adderN.rtlv.hdb
........\..\adderN.fnsim.qmsg
........\..\adderN.rtlv_sg_swap.cdb
........\..\adderN.pre_map.hdb
........\..\adderN.pre_map.cdb
........\..\adderN.psp
........\..\adderN.dbp
........\..\adderN.map.logdb
........\..\adderN.sgdiff.cdb
........\..\adderN.sgdiff.hdb
........\..\adderN.syn_hier_info
........\..\adderN.map.cdb
........\..\adderN.map.hdb
........\..\adderN.cmp0.ddb
........\..\adderN.fit.qmsg
........\..\adderN.cmp.logdb
........\..\adderN.cmp.cdb
........\..\adderN.signalprobe.cdb
........\..\adderN.sim.hdb
........\..\adderN.cmp.kpt
........\..\adderN.cmp.hdb
........\..\adderN.cmp.rdb
........\..\adderN.fnsim.cdb
........\..\adderN.asm.qmsg
........\..\adderN.fnsim.hdb
........\..\adderN.sld_design_entry_dsc.sci
........\..\adderN.eds_overflow
........\..\adderN.sim.vwf
........\..\adderN.sim.rdb
........\..\wed.zsf
........\..\adderN.rpp.qmsg
........\..\adderN.sgate.rvd
........\..\adderN.sgate_sm.rvd
........\..\adderN.sld_design_entry.sci
........\..\adderN.eco.cdb
........\db
........\adderN.vhd
........\adderN.map.rpt
........\adderN.flow.rpt
........\adderN.map.summary
........\adderN.pin
........\adderN.fit.rpt
........\adderN.fit.smsg
........\adderN.fit.summary
........\adderN.done
5vadderN

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