The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes

dcm1\.lso
....\chip.cdc
....\dcm1.bgn
....\dcm1.bit
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....\dcm1.ptwx
....\dcm1.restore
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....\dcm1.syr
....\dcm1.twr
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....\dcm1_map.map
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....\dcm1_prev_built.ngd
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....\fangzhen.fdo
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....\......\netgen.xmsgs
....\......\ngdbuild.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
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....\.ngo\dcm1_cs_signalbrowser.ngo
....\....\dcm1_cs_signalbrowser.ver
....\....\icon_pro.ncf
....\....\icon_pro.ngc
....\....\ila_pro_0.ncf
....\....\ila_pro_0.ngc
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....\....\cs_ila_pro_0\coregen.cgp
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....\....\............\ila_pro_0.cdc
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....\....\............\xlnx_auto_0.ise
....\....\............\..........._xdb\tmp\ise.lock
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....\....\............\...............\...\...\............\Autonym\regkeys
....\....\....con_pro\coregen.cgp
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....\....\...........\generate_icon_pro.xco
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....\....\...........\icon_pro.vho
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