cpu code 。。。。。。。。。。。。。。。。

cpuzuizhong1\ALU.v
............\ban_reg.v
............\counter.v
............\cpuucf.ucf
............\cpuyueshu.cel
............\cpuzuizhong.ise
............\cpuzuizhong.ise_ISE_Backup
............\cpuzuizhong.ntrc_log
............\cpuzuizhong.restore
............\CPU_ucf.cel
............\CU.v
............\div.v
............\EX.v
............\final_test.v
............\final_test_v.fdo
............\final_test_v.udo
............\GR.v
............\IF.v
............\KD_CPU.cmd_log
............\KD_CPU.lso
............\KD_CPU.ngc
............\KD_CPU.ngr
............\KD_CPU.prj
............\KD_CPU.stx
............\KD_CPU.syr
............\KD_CPU.v
............\KD_CPU.xst
............\KD_CPU_summary.html
............\memory.v
............\mul.v
............\multiply.v
............\MUSIC.v
............\mux16.v
............\mux2.v
............\mux4.v
............\PC.v
............\register_template.v
............\require_reg.v
............\SP.v
............\test.v
............\transcript
............\vsim.wlf
............\work\@a@l@u\verilog.asm
............\....\......\_primary.dat
............\....\......\_primary.vhd
............\....\.c@u\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\.e@x\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\.g@r\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\.i@f\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\.k@d_@c@p@u\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\.m@u@s@i@c\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\.p@c\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\.s@p\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\ban_reg\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\counter\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\div\verilog.asm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\final_test_v\verilog.asm
............\....\............\_primary.dat
............\....\............\_primary.vhd
............\....\glbl\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\memory\verilog.asm
............\....\......\_primary.dat
............\....\......\_primary.vhd
............\....\.ul\verilog.asm
............\....\...\_primary.dat
............\....\...\_primary.vhd
............\....\..x16\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\...2\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\...4\verilog.asm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\register_template\verilog.asm

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