A technology Divider, 5-band case, Verilog source code

div_5
.....\div_5.cr.mti
.....\div_5.mpf
.....\div_5.v
.....\div_5.v.bak
.....\vsim.wlf
.....\work
.....\....\div
.....\....\...\verilog.asm
.....\....\...\verilog.rw
.....\....\...\_primary.dat
.....\....\...\_primary.dbs
.....\....\...\_primary.vhd
.....\....\div_5
.....\....\.....\verilog.asm
.....\....\.....\verilog.rw
.....\....\.....\_primary.dat
.....\....\.....\_primary.dbs
.....\....\.....\_primary.vhd
.....\....\for_clk
.....\....\.......\verilog.asm
.....\....\.......\verilog.rw
.....\....\.......\_primary.dat
.....\....\.......\_primary.dbs
.....\....\.......\_primary.vhd
.....\....\test
.....\....\....\verilog.asm
.....\....\....\verilog.rw
.....\....\....\_primary.dat
.....\....\....\_primary.dbs
.....\....\....\_primary.vhd
.....\....\_info
.....\....\_temp
.....\....\.....\vlog0r0wzw
.....\....\.....\vlog1c76vk
.....\....\.....\vlog1kbqc0
.....\....\.....\vlog2zwdeb
.....\....\.....\vlogabkkgn
.....\....\.....\vlogb22t0s
.....\....\.....\vlogb76yy6
.....\....\.....\vlogdbeahj
.....\....\.....\vlogg582vk
.....\....\.....\vlogg5xjzd
.....\....\.....\vloggcc2ej
.....\....\.....\vloggyfjci
.....\....\.....\vlogmd689x
.....\....\.....\vlogs4mrfy
.....\....\.....\vlogsksrzw
.....\....\.....\vlogsqs1i0
.....\....\.....\vlogsrjngz
.....\....\.....\vlogsx9r9m
.....\....\.....\vlogwj6x27
.....\....\.....\vlogxhrc2c
.....\....\_vmake

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