a simple vga verilog fgpa test

round\db\prev_cmp_round.qmsg
.....\..\round.cbx.xml
.....\..\round.cmp.rdb
.....\..\round.db_info
.....\..\round.eco.cdb
.....\..\round.hier_info
.....\..\round.hif
.....\..\round.lpc.html
.....\..\round.lpc.rdb
.....\..\round.lpc.txt
.....\..\round.map.qmsg
.....\..\round.pre_map.cdb
.....\..\round.pre_map.hdb
.....\..\round.rtlv.hdb
.....\..\round.rtlv_sg.cdb
.....\..\round.rtlv_sg_swap.cdb
.....\..\round.sld_design_entry.sci
.....\incremental_db\compiled_partitions\round.root_partition.map.dpi.tmp
.....\..............\README
.....\round.qpf
.....\round.qsf
.....\round.qws
.....\round.v
.....\incremental_db\compiled_partitions
.....\db
.....\incremental_db
round

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