this is verilog model of RISC CPU

lab10\.simvision\dbrowser-bookmarks
.....\..........\schematic-bookmarks
.....\..........\source-bookmarks
.....\aasd.v
.....\aasd.v~
.....\alu.v
.....\alu.v~
.....\clk_gen.v
.....\clk_gen.v~
.....\control.v
.....\control.v~
.....\counter.v
.....\counter.v~
.....\cpu.v
.....\cpu.v~
.....\INCA_libs\irun.lnx86.08.20.nc\.ncrun.lock
.....\.........\...................\.ncv.lock
.....\.........\...................\bind.lst.lnx86
.....\.........\...................\cds.lib
.....\.........\...................\cdsrun.lib
.....\.........\...................\dcd144.ecs.csun.edu_19944\ncsim.args
.....\.........\...................\.........................\ncsim.env
.....\.........\...................\.........................\ncverilog.args
.....\.........\...................\....................20811\ncsim.args
.....\.........\...................\.........................\ncsim.env
.....\.........\...................\.........................\ncverilog.args
.....\.........\...................\.....................1494\ncsim.args
.....\.........\...................\.........................\ncsim.env
.....\.........\...................\.........................\ncverilog.args
.....\.........\...................\files.ts
.....\.........\...................\hdl.var
.....\.........\...................\hdlrun.var
.....\.........\...................\ncelab.args
.....\.........\...................\ncelab.env
.....\.........\...................\ncelab.hrd
.....\.........\...................\ncsim.args
.....\.........\...................\ncsim.env
.....\.........\...................\ncsim_restart.args
.....\.........\...................\ncsim_restart.env
.....\.........\...................\ncverilog.args
.....\.........\...................\ncvlog.args
.....\.........\...................\ncvlog.env
.....\.........\...................\ncvlog.files
.....\.........\snap.nc\.ncrun.lock
.....\.........\.......\.ncv.lock
.....\.........\.......\bind.lst.lnx86
.....\.........\.......\cds.lib
.....\.........\.......\cdsrun.lib
.....\.........\.......\dcd144.ecs.csun.edu_19944\ncsim.args
.....\.........\.......\.........................\ncsim.env
.....\.........\.......\.........................\ncverilog.args
.....\.........\.......\....................20811\ncsim.args
.....\.........\.......\.........................\ncsim.env
.....\.........\.......\.........................\ncverilog.args
.....\.........\.......\.....................1494\ncsim.args
.....\.........\.......\.........................\ncsim.env
.....\.........\.......\.........................\ncverilog.args
.....\.........\.......\files.ts
.....\.........\.......\hdl.var
.....\.........\.......\hdlrun.var
.....\.........\.......\ncelab.args
.....\.........\.......\ncelab.env
.....\.........\.......\ncelab.hrd
.....\.........\.......\ncsim.args
.....\.........\.......\ncsim.env
.....\.........\.......\ncsim_restart.args
.....\.........\.......\ncsim_restart.env
.....\.........\.......\ncverilog.args
.....\.........\.......\ncvlog.args
.....\.........\.......\ncvlog.env
.....\.........\.......\ncvlog.files
.....\.........\worklib\.cdsvmod
.....\.........\.......\.inca.db.169.lnx86
.....\.........\.......\cdsinfo.tag
.....\.........\.......\inca.lnx86.169.pak
.....\mem_file.txt
.....\mem_file.txt~
.....\ncverilog.key
.....\ncverilog.log
.....\ram.v
.....\ram.v~
.....\register.v
.....\register.v~
.....\risedge.v
.....\risedge.v~
.....\run.f
.....\run.f~
.....\scale_mux.v
.....\scale_mux.v~
.....\tb_cpu.v
.....\tb_cpu.v~
.....\tb_risedge.v
.....\tb_risedge.v~
.....\waves.shm\waves.dsn
.....\.........\waves.trn
.....\xyz.v
.....\xyz.v~
.....\INCA_libs\irun.lnx86.08.20.nc\dcd144.ecs.csun.edu_19944
.....\.........\...................\dcd144.ecs.csun.edu_20811
.....\.........\...................\dcd144.ecs.csun.edu_21494

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