Verilog HDL design with a multi-functional digital clock, includes the following main functions: (1) time, time to 24-hour display. (2) school, (3) stopwatch: start, stop, pause

digital_clock\bin27seg.bsf
.............\bin27seg.v
.............\clk_s.bsf
.............\clk_s.v
.............\clock_1khz.bsf
.............\clock_1khz.v
.............\db\add_sub_7rh.tdf
.............\..\add_sub_8rh.tdf
.............\..\add_sub_ke8.tdf
.............\..\add_sub_le8.tdf
.............\..\add_sub_ma8.tdf
.............\..\add_sub_me8.tdf
.............\..\add_sub_msh.tdf
.............\..\add_sub_ne8.tdf
.............\..\add_sub_nsh.tdf
.............\..\add_sub_oe8.tdf
.............\..\alt_u_div_hld.tdf
.............\..\cntr_gud.tdf
.............\..\digital_clock.asm.qmsg
.............\..\digital_clock.cbx.xml
.............\..\digital_clock.cmp.cdb
.............\..\digital_clock.cmp.hdb
.............\..\digital_clock.cmp.qrpt
.............\..\digital_clock.cmp.rdb
.............\..\digital_clock.cmp.tdb
.............\..\digital_clock.cmp0.ddb
.............\..\digital_clock.dbp
.............\..\digital_clock.db_info
.............\..\digital_clock.eco.cdb
.............\..\digital_clock.eds_overflow
.............\..\digital_clock.fit.qmsg
.............\..\digital_clock.fnsim.cdb
.............\..\digital_clock.fnsim.hdb
.............\..\digital_clock.fnsim.qmsg
.............\..\digital_clock.hier_info
.............\..\digital_clock.hif
.............\..\digital_clock.map.cdb
.............\..\digital_clock.map.hdb
.............\..\digital_clock.map.qmsg
.............\..\digital_clock.pre_map.cdb
.............\..\digital_clock.pre_map.hdb
.............\..\digital_clock.psp
.............\..\digital_clock.rtlv.hdb
.............\..\digital_clock.rtlv_sg.cdb
.............\..\digital_clock.rtlv_sg_swap.cdb
.............\..\digital_clock.sgdiff.cdb
.............\..\digital_clock.sgdiff.hdb
.............\..\digital_clock.signalprobe.cdb
.............\..\digital_clock.sim.hdb
.............\..\digital_clock.sim.qmsg
.............\..\digital_clock.sim.qrpt
.............\..\digital_clock.sim.rdb
.............\..\digital_clock.sim.vwf
.............\..\digital_clock.sld_design_entry.sci
.............\..\digital_clock.sld_design_entry_dsc.sci
.............\..\digital_clock.smp_dump.txt
.............\..\digital_clock.syn_hier_info
.............\..\digital_clock.tan.qmsg
.............\..\lpm_divide_klf.tdf
.............\..\lpm_divide_ndf.tdf
.............\..\mux_9fc.tdf
.............\..\sign_div_unsign_mhg.tdf
.............\delay.bsf
.............\delay.v
.............\digital_clock.asm.rpt
.............\digital_clock.bdf
.............\digital_clock.cdf
.............\digital_clock.done
.............\digital_clock.fit.eqn
.............\digital_clock.fit.rpt
.............\digital_clock.fit.summary
.............\digital_clock.flow.rpt
.............\digital_clock.map.eqn
.............\digital_clock.map.rpt
.............\digital_clock.map.summary
.............\digital_clock.pin
.............\digital_clock.pof
.............\digital_clock.qpf
.............\digital_clock.qsf
.............\digital_clock.qws
.............\digital_clock.sim.rpt
.............\digital_clock.sof
.............\digital_clock.tan.rpt
.............\digital_clock.tan.summary
.............\digital_clock.vwf
.............\dp.bsf
.............\dp.v
.............\fangdou.bsf
.............\fangdou.v
.............\key_filter.bsf
.............\key_filter.v
.............\key_min.bsf
.............\key_min.v
.............\lpm_counter0.bsf
.............\lpm_counter0.v
.............\lpm_counter0_bb.v
.............\lpm_counter0_wave0.jpg
.............\lpm_counter0_waveforms.html
.............\lpm_counter1.bsf
.............\lpm_counter1.v

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