This implements an asynchronous fifo, by synchronizing the asynchronous method into a synchronous fifo fifo to achieve, simplifying the hardware implementation of the project

sync_fifo\dp_ram.v
.........\wlftnah16m
.........\aaaa.cr.mti
.........\aaaa.mpf
.........\sync_fifo.v
.........\sync_fifo2.v
.........\t_fifo.v
.........\makefile
.........\work\_info
.........\....\.temp\vlogateb2h
.........\....\.....\vlognd0srx
.........\....\.....\vlogs8jyri
.........\....\.....\vlogn15swh
.........\....\.....\vlog9y88qj
.........\....\.....\vlog9nzrsd
.........\....\.....\vlogyakakb
.........\....\.....\vlogen37hx
.........\....\.....\vlog73q009
.........\....\_vmake
.........\....\dp_ram\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\verilog.rw
.........\....\......\_primary.dbs
.........\....\......\_primary.dat
.........\....\t_fifo\_primary.vhd
.........\....\......\verilog.asm
.........\....\......\verilog.rw
.........\....\......\_primary.dbs
.........\....\......\_primary.dat
.........\....\sync_fifo\_primary.vhd
.........\....\.........\verilog.asm
.........\....\.........\verilog.rw
.........\....\.........\_primary.dbs
.........\....\.........\_primary.dat
.........\transcript
.........\vsim.wlf
.........\work\_temp
.........\....\dp_ram
.........\....\t_fifo
.........\....\sync_fifo
.........\work
sync_fifo

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