sample of VHDL coding

assignment 1 part 1\CAD1_part1.asm.rpt
...................\CAD1_part1.done
...................\CAD1_part1.fit.rpt
...................\CAD1_part1.fit.summary
...................\CAD1_part1.flow.rpt
...................\CAD1_part1.map.rpt
...................\CAD1_part1.map.summary
...................\CAD1_part1.pin
...................\CAD1_part1.pof
...................\CAD1_part1.qpf
...................\CAD1_part1.qsf
...................\CAD1_part1.qws
...................\CAD1_part1.sim.rpt
...................\CAD1_part1.sof
...................\CAD1_part1.tan.rpt
...................\CAD1_part1.tan.summary
...................\CAD1_part1_1.pof
...................\CAD1_part1_description.txt
...................\db
...................\..\CAD1_part1.asm.qmsg
...................\..\CAD1_part1.atom.rvd
...................\..\CAD1_part1.cbx.xml
...................\..\CAD1_part1.cmp.cdb
...................\..\CAD1_part1.cmp.hdb
...................\..\CAD1_part1.cmp.logdb
...................\..\CAD1_part1.cmp.rdb
...................\..\CAD1_part1.cmp.tdb
...................\..\CAD1_part1.cmp0.ddb
...................\..\CAD1_part1.db_info
...................\..\CAD1_part1.eco.cdb
...................\..\CAD1_part1.eds_overflow
...................\..\CAD1_part1.fit.qmsg
...................\..\CAD1_part1.fnsim.cdb
...................\..\CAD1_part1.fnsim.hdb
...................\..\CAD1_part1.fnsim.qmsg
...................\..\CAD1_part1.hier_info
...................\..\CAD1_part1.hif
...................\..\CAD1_part1.lpc.html
...................\..\CAD1_part1.lpc.rdb
...................\..\CAD1_part1.lpc.txt
...................\..\CAD1_part1.map.cdb
...................\..\CAD1_part1.map.hdb
...................\..\CAD1_part1.map.logdb
...................\..\CAD1_part1.map.qmsg
...................\..\CAD1_part1.pre_map.cdb
...................\..\CAD1_part1.pre_map.hdb
...................\..\CAD1_part1.rpp.qmsg
...................\..\CAD1_part1.rtlv.hdb
...................\..\CAD1_part1.rtlv_sg.cdb
...................\..\CAD1_part1.rtlv_sg_swap.cdb
...................\..\CAD1_part1.sgdiff.cdb
...................\..\CAD1_part1.sgdiff.hdb
...................\..\CAD1_part1.signalprobe.cdb
...................\..\CAD1_part1.sim.cvwf
...................\..\CAD1_part1.sim.hdb
...................\..\CAD1_part1.sim.qmsg
...................\..\CAD1_part1.sim.rdb
...................\..\CAD1_part1.simfam
...................\..\CAD1_part1.sld_design_entry.sci
...................\..\CAD1_part1.sld_design_entry_dsc.sci
...................\..\CAD1_part1.syn_hier_info
...................\..\CAD1_part1.tan.qmsg
...................\..\CAD1_part1.tis_db_list.ddb
...................\..\CAD1_part1.tmw_info
...................\..\prev_cmp_CAD1_part1.asm.qmsg
...................\..\prev_cmp_CAD1_part1.fit.qmsg
...................\..\prev_cmp_CAD1_part1.map.qmsg
...................\..\prev_cmp_CAD1_part1.qmsg
...................\..\prev_cmp_CAD1_part1.sim.qmsg
...................\..\prev_cmp_CAD1_part1.tan.qmsg
...................\..\wed.wsf
...................\FA.vhd
...................\full_adder.vwf
...................\half adder.vhd
...................\half adder.vhd.bak
...................\half_adder.vwf
...................\incremental_db
...................\..............\compiled_partitions
...................\..............\...................\CAD1_part1.root_partition.map.kpt
...................\..............\README

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