Risc cpu simple design, I code by the book, but also added some, has been through simulation.

RISC_SPM\work\_info
........\....\_vmake
........\....\@r@i@s@c_@s@p@m\_primary.vhd
........\....\...............\_primary.dbs
........\....\...............\_primary.dat
........\....\...............\verilog.asm
........\....\...............\verilog.rw
........\....\.processing_@unit\_primary.vhd
........\....\.................\_primary.dbs
........\....\.................\_primary.dat
........\....\.................\verilog.asm
........\....\.................\verilog.rw
........\....\.register_@unit\_primary.vhd
........\....\...............\_primary.dbs
........\....\...............\_primary.dat
........\....\...............\verilog.asm
........\....\...............\verilog.rw
........\....\.d_flop\_primary.vhd
........\....\.......\_primary.dbs
........\....\.......\_primary.dat
........\....\.......\verilog.asm
........\....\.......\verilog.rw
........\....\.address_@register\_primary.vhd
........\....\..................\_primary.dbs
........\....\..................\_primary.dat
........\....\..................\verilog.asm
........\....\..................\verilog.rw
........\....\.instruction_@register\_primary.vhd
........\....\......................\_primary.dbs
........\....\......................\_primary.dat
........\....\......................\verilog.asm
........\....\......................\verilog.rw
........\....\.program_@counter\_primary.vhd
........\....\.................\_primary.dbs
........\....\.................\_primary.dat
........\....\.................\verilog.asm
........\....\.................\verilog.rw
........\....\.multiplexer_5ch\_primary.vhd
........\....\................\_primary.dbs
........\....\................\_primary.dat
........\....\................\verilog.asm
........\....\................\verilog.rw
........\....\.............3ch\_primary.vhd
........\....\................\_primary.dbs
........\....\................\_primary.dat
........\....\................\verilog.asm
........\....\................\verilog.rw
........\....\.alu_@r@i@s@c\_primary.vhd
........\....\.............\_primary.dbs
........\....\.............\_primary.dat
........\....\.............\verilog.asm
........\....\.............\verilog.rw
........\....\.control_@unit\_primary.vhd
........\....\..............\_primary.dbs
........\....\..............\_primary.dat
........\....\..............\verilog.asm
........\....\..............\verilog.rw
........\....\.memory_@unit\_primary.vhd
........\....\.............\_primary.dbs
........\....\.............\_primary.dat
........\....\.............\verilog.asm
........\....\.............\verilog.rw
........\....\test_@r@i@s@c_@s@p@m\_primary.vhd
........\....\....................\_primary.dbs
........\....\....................\_primary.dat
........\....\....................\verilog.asm
........\....\....................\verilog.rw
........\....\@clock_@unit\_primary.vhd
........\....\............\_primary.dbs
........\....\............\_primary.dat
........\....\............\verilog.asm
........\....\............\verilog.rw
........\RISC_SPM.v
........\test_RISC_SPM.v
........\RISC_SPM.v.bak
........\Clock_Unit.v
........\vsim.wlf
........\test_RISC_SPM.v.bak
........\RISC_SPM.mpf
........\RISC_SPM.cr.mti
........\work\_temp
........\....\@r@i@s@c_@s@p@m
........\....\@processing_@unit
........\....\@register_@unit
........\....\@d_flop
........\....\@address_@register
........\....\@instruction_@register
........\....\@program_@counter
........\....\@multiplexer_5ch
........\....\@multiplexer_3ch
........\....\@alu_@r@i@s@c
........\....\@control_@unit
........\....\@memory_@unit
........\....\test_@r@i@s@c_@s@p@m
........\....\@clock_@unit
........\work
RISC_SPM

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