When learning to write their own fpga small test program. People can see the new entry, studies. The front part of a fpga1, follow-up has fpga3, and personal experience.

fpga2\test5\test5.qpf
.....\.....\test5.qsf
.....\.....\test5.vhd
.....\.....\test5.map.summary
.....\.....\test5.map.rpt
.....\.....\test5.flow.rpt
.....\.....\test5.done
.....\.....\test5.vwf
.....\.....\test5.sim.rpt
.....\.....\test5.qws
.....\.....\db\test5.db_info
.....\.....\..\test5.map.qmsg
.....\.....\..\test5.cbx.xml
.....\.....\..\test5.hif
.....\.....\..\test5.hier_info
.....\.....\..\test5.rtlv_sg.cdb
.....\.....\..\test5.rtlv.hdb
.....\.....\..\test5.rtlv_sg_swap.cdb
.....\.....\..\test5.pre_map.hdb
.....\.....\..\test5.pre_map.cdb
.....\.....\..\test5.psp
.....\.....\..\test5.dbp
.....\.....\..\test5.pss
.....\.....\..\test5.map_bb.logdb
.....\.....\..\test5.sgdiff.cdb
.....\.....\..\test5.sgdiff.hdb
.....\.....\..\test5.syn_hier_info
.....\.....\..\test5.map_bb.cdb
.....\.....\..\test5.map_bb.hdb
.....\.....\..\test5.map.ecobp
.....\.....\..\test5.map.cdb
.....\.....\..\test5.map.hdb
.....\.....\..\test5.map.logdb
.....\.....\..\test5.map.bpm
.....\.....\..\test5.cmp.rdb
.....\.....\..\test5.tis_db_list.ddb
.....\.....\..\test5.fnsim.qmsg
.....\.....\..\mux_cfc.tdf
.....\.....\..\test5.fnsim.cdb
.....\.....\..\test5.fnsim.hdb
.....\.....\..\test5.sld_design_entry_dsc.sci
.....\.....\..\prev_cmp_test5.qmsg
.....\.....\..\test5.sim.qmsg
.....\.....\..\test5.sim.hdb
.....\.....\..\test5.simfam
.....\.....\..\test5.eds_overflow
.....\.....\..\test5.sim.cvwf
.....\.....\..\test5.sim.rdb
.....\.....\..\test5.sld_design_entry.sci
.....\.....\..\wed.wsf
.....\.....\..\test5.eco.cdb
.....\....1\test1.qpf
.....\.....\test1.qsf
.....\.....\test1.map.summary
.....\.....\test1.pin
.....\.....\test1.fit.smsg
.....\.....\test1.fit.summary
.....\.....\test1.tan.summary
.....\.....\test1.done
.....\.....\test1.dpf
.....\.....\test1.vwf
.....\.....\test1.fit.rpt
.....\.....\test1.asm.rpt
.....\.....\test1.tan.rpt
.....\.....\Waveform1.vwf
.....\.....\test1.vhd.bak
.....\.....\test1.vhd
.....\.....\test1.map.rpt
.....\.....\test1.flow.rpt
.....\.....\test1.sim.rpt
.....\.....\test1.qws
.....\.....\db\mux_cfc.tdf
.....\.....\..\test1.db_info
.....\.....\..\test1.map_bb.logdb
.....\.....\..\test1.sgdiff.cdb
.....\.....\..\test1.sgdiff.hdb
.....\.....\..\prev_cmp_test1.sim.qmsg
.....\.....\..\prev_cmp_test1.qmsg
.....\.....\..\test1.sim.qmsg
.....\.....\..\test1.fit.qmsg
.....\.....\..\test1.cbx.xml
.....\.....\..\test1.hif
.....\.....\..\test1.hier_info
.....\.....\..\test1.sld_design_entry.sci
.....\.....\..\test1.rtlv_sg_swap.cdb
.....\.....\..\test1.cmp0.ddb
.....\.....\..\test1.cmp.rdb
.....\.....\..\test1.pre_map.hdb
.....\.....\..\test1.psp
.....\.....\..\test1.dbp
.....\.....\..\test1.pss
.....\.....\..\test1.pre_map.cdb
.....\.....\..\test1.asm.qmsg
.....\.....\..\test1.eco.cdb
.....\.....\..\prev_cmp_test1.map.qmsg
.....\.....\..\test1.sim.hdb
.....\.....\..\test1.syn_hier_info
.....\.....\..\test1.tan.qmsg
.....\.....\..\test1.sim.rdb
.....\.....\..\test1.rtlv.hdb

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