Digital clock modular circuit -

CLOCK\CLOCK.asm.rpt
.....\CLOCK.bdf
.....\CLOCK.cdf
.....\CLOCK.done
.....\CLOCK.dpf
.....\CLOCK.fit.rpt
.....\CLOCK.fit.smsg
.....\CLOCK.fit.summary
.....\CLOCK.flow.rpt
.....\CLOCK.map.rpt
.....\CLOCK.map.summary
.....\CLOCK.pin
.....\CLOCK.pof
.....\CLOCK.qpf
.....\CLOCK.qsf
.....\CLOCK.qws
.....\CLOCK.sim.rpt
.....\CLOCK.sof
.....\CLOCK.tan.rpt
.....\CLOCK.tan.summary
.....\CLOCK.vwf
.....\CLOCK_assignment_defaults.qdf
.....\db\CLOCK.asm.qmsg
.....\..\CLOCK.cbx.xml
.....\..\CLOCK.cmp.cdb
.....\..\CLOCK.cmp.hdb
.....\..\CLOCK.cmp.logdb
.....\..\CLOCK.cmp.rdb
.....\..\CLOCK.cmp.tdb
.....\..\CLOCK.cmp0.ddb
.....\..\CLOCK.dbp
.....\..\CLOCK.db_info
.....\..\CLOCK.eco.cdb
.....\..\CLOCK.fit.qmsg
.....\..\CLOCK.hier_info
.....\..\CLOCK.hif
.....\..\CLOCK.map.cdb
.....\..\CLOCK.map.hdb
.....\..\CLOCK.map.logdb
.....\..\CLOCK.map.qmsg
.....\..\CLOCK.pre_map.cdb
.....\..\CLOCK.pre_map.hdb
.....\..\CLOCK.psp
.....\..\CLOCK.pss
.....\..\CLOCK.rtlv.hdb
.....\..\CLOCK.rtlv_sg.cdb
.....\..\CLOCK.rtlv_sg_swap.cdb
.....\..\CLOCK.sgdiff.cdb
.....\..\CLOCK.sgdiff.hdb
.....\..\CLOCK.signalprobe.cdb
.....\..\CLOCK.sld_design_entry.sci
.....\..\CLOCK.sld_design_entry_dsc.sci
.....\..\CLOCK.syn_hier_info
.....\..\CLOCK.tan.qmsg
.....\..\CLOCK.tis_db_list.ddb
.....\..\prev_cmp_CLOCK.asm.qmsg
.....\..\prev_cmp_CLOCK.fit.qmsg
.....\..\prev_cmp_CLOCK.map.qmsg
.....\..\prev_cmp_CLOCK.qmsg
.....\..\prev_cmp_CLOCK.tan.qmsg
.....\..\wed.zsf
.....\lpm_and0.bsf
.....\lpm_and0.cmp
.....\lpm_and0.vhd
.....\lpm_and1.bsf
.....\lpm_and1.cmp
.....\lpm_and1.vhd
.....\lpm_and2.bsf
.....\lpm_and2.inc
.....\lpm_and2.vhd
.....\lpm_and6.bsf
.....\lpm_and6.cmp
.....\lpm_and6.vhd
.....\lpm_inv0.bsf
.....\lpm_inv0.cmp
.....\lpm_inv0.vhd
.....\lpm_or0.bsf
.....\lpm_or0.cmp
.....\lpm_or0.vhd
.....\lpm_or1.bsf
.....\lpm_or1.cmp
.....\lpm_or1.vhd
.....\lpm_or6.bsf
.....\lpm_or6.inc
.....\lpm_or6.vhd
.....\db
CLOCK

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