Functions to achieve 74hc151 with Verilog.

74hc151\db\logic_util_heursitic.dat
.......\..\mux8_1.asm.qmsg
.......\..\mux8_1.asm.rdb
.......\..\mux8_1.asm_labs.ddb
.......\..\mux8_1.cbx.xml
.......\..\mux8_1.cmp.cdb
.......\..\mux8_1.cmp.hdb
.......\..\mux8_1.cmp.kpt
.......\..\mux8_1.cmp.logdb
.......\..\mux8_1.cmp.rdb
.......\..\mux8_1.cmp.tdb
.......\..\mux8_1.cmp0.ddb
.......\..\mux8_1.db_info
.......\..\mux8_1.eco.cdb
.......\..\mux8_1.eda.qmsg
.......\..\mux8_1.fit.qmsg
.......\..\mux8_1.hier_info
.......\..\mux8_1.hif
.......\..\mux8_1.lpc.html
.......\..\mux8_1.lpc.rdb
.......\..\mux8_1.lpc.txt
.......\..\mux8_1.map.cdb
.......\..\mux8_1.map.hdb
.......\..\mux8_1.map.logdb
.......\..\mux8_1.map.qmsg
.......\..\mux8_1.pre_map.cdb
.......\..\mux8_1.pre_map.hdb
.......\..\mux8_1.rtlv.hdb
.......\..\mux8_1.rtlv_sg.cdb
.......\..\mux8_1.rtlv_sg_swap.cdb
.......\..\mux8_1.sgdiff.cdb
.......\..\mux8_1.sgdiff.hdb
.......\..\mux8_1.sld_design_entry.sci
.......\..\mux8_1.sld_design_entry_dsc.sci
.......\..\mux8_1.smart_action.txt
.......\..\mux8_1.syn_hier_info
.......\..\mux8_1.tan.qmsg
.......\..\mux8_1.tis_db_list.ddb
.......\..\mux8_1.tmw_info
.......\..\prev_cmp_mux8_1.asm.qmsg
.......\..\prev_cmp_mux8_1.eda.qmsg
.......\..\prev_cmp_mux8_1.fit.qmsg
.......\..\prev_cmp_mux8_1.map.qmsg
.......\..\prev_cmp_mux8_1.qmsg
.......\..\prev_cmp_mux8_1.tan.qmsg
.......\incremental_db\compiled_partitions\mux8_1.root_partition.map.kpt
.......\..............\README
.......\mux8_1.asm.rpt
.......\mux8_1.done
.......\mux8_1.dpf
.......\mux8_1.eda.rpt
.......\mux8_1.fit.rpt
.......\mux8_1.fit.summary
.......\mux8_1.flow.rpt
.......\mux8_1.map.rpt
.......\mux8_1.map.summary
.......\mux8_1.pin
.......\mux8_1.pof
.......\mux8_1.qpf
.......\mux8_1.qsf
.......\mux8_1.qws
.......\mux8_1.tan.rpt
.......\mux8_1.tan.summary
.......\mux8_1.v
.......\mux8_1.v.bak
.......\mux8_1_nativelink_simulation.rpt
.......\simulation\modelsim\modelsim.ini
.......\..........\........\msim_transcript
.......\..........\........\mux8_1.sft
.......\..........\........\mux8_1.vo
.......\..........\........\mux8_1.vt
.......\..........\........\mux8_1.vt.bak
.......\..........\........\mux8_1_modelsim.xrf
.......\..........\........\mux8_1_run_msim_rtl_verilog.do
.......\..........\........\mux8_1_v.sdo
.......\..........\........\rtl_work\mux8_1\verilog.prw
.......\..........\........\........\......\verilog.psm
.......\..........\........\........\......\_primary.dat
.......\..........\........\........\......\_primary.dbs
.......\..........\........\........\......\_primary.vhd
.......\..........\........\........\testbench\verilog.prw
.......\..........\........\........\.........\verilog.psm
.......\..........\........\........\.........\_primary.dat
.......\..........\........\........\.........\_primary.dbs
.......\..........\........\........\.........\_primary.vhd
.......\..........\........\........\_info
.......\..........\........\........\_vmake
.......\..........\........\vsim.wlf
.......\..........\........\rtl_work\mux8_1
.......\..........\........\........\testbench
.......\..........\........\........\_temp
.......\..........\........\rtl_work
.......\incremental_db\compiled_partitions
.......\simulation\modelsim
.......\db
.......\incremental_db
.......\simulation
74hc151

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