The purpose of this project is to design a simple Processor Unit

processor
.........\db
.........\..\add_sub_0qh.tdf
.........\..\add_sub_1qh.tdf
.........\..\add_sub_2sh.tdf
.........\..\add_sub_vrh.tdf
.........\..\altsyncram_81b1.tdf
.........\..\altsyncram_pca1.tdf
.........\..\mux_egc.tdf
.........\..\mux_jgc.tdf
.........\..\prev_cmp_processor.asm.qmsg
.........\..\prev_cmp_processor.fit.qmsg
.........\..\prev_cmp_processor.map.qmsg
.........\..\prev_cmp_processor.qmsg
.........\..\prev_cmp_processor.sim.qmsg
.........\..\prev_cmp_processor.tan.qmsg
.........\..\processor.asm.qmsg
.........\..\processor.cbx.xml
.........\..\processor.cmp.bpm
.........\..\processor.cmp.cdb
.........\..\processor.cmp.ecobp
.........\..\processor.cmp.hdb
.........\..\processor.cmp.kpt
.........\..\processor.cmp.logdb
.........\..\processor.cmp.rdb
.........\..\processor.cmp.tdb
.........\..\processor.cmp0.ddb
.........\..\processor.cmp_merge.kpt
.........\..\processor.db_info
.........\..\processor.eco.cdb
.........\..\processor.eds_overflow
.........\..\processor.fit.qmsg
.........\..\processor.fnsim.cdb
.........\..\processor.fnsim.hdb
.........\..\processor.fnsim.qmsg
.........\..\processor.hier_info
.........\..\processor.hif
.........\..\processor.lpc.html
.........\..\processor.lpc.rdb
.........\..\processor.lpc.txt
.........\..\processor.map.bpm
.........\..\processor.map.cdb
.........\..\processor.map.ecobp
.........\..\processor.map.hdb
.........\..\processor.map.kpt
.........\..\processor.map.logdb
.........\..\processor.map.qmsg
.........\..\processor.map_bb.cdb
.........\..\processor.map_bb.hdb
.........\..\processor.map_bb.logdb
.........\..\processor.pre_map.cdb
.........\..\processor.pre_map.hdb
.........\..\processor.rtlv.hdb
.........\..\processor.rtlv_sg.cdb
.........\..\processor.rtlv_sg_swap.cdb
.........\..\processor.sgdiff.cdb
.........\..\processor.sgdiff.hdb
.........\..\processor.sim.cvwf
.........\..\processor.sim.hdb
.........\..\processor.sim.qmsg
.........\..\processor.sim.rdb
.........\..\processor.simfam
.........\..\processor.sld_design_entry.sci
.........\..\processor.sld_design_entry_dsc.sci
.........\..\processor.syn_hier_info
.........\..\processor.tan.qmsg
.........\..\processor.tis_db_list.ddb
.........\..\processor.tmw_info
.........\..\processor_global_asgn_op.abo
.........\..\wed.wsf
.........\incremental_db
.........\..............\compiled_partitions
.........\..............\...................\processor.root_partition.cmp.atm
.........\..............\...................\processor.root_partition.cmp.dfp
.........\..............\...................\processor.root_partition.cmp.hdbx
.........\..............\...................\processor.root_partition.cmp.kpt
.........\..............\...................\processor.root_partition.cmp.logdb
.........\..............\...................\processor.root_partition.cmp.rcf
.........\..............\...................\processor.root_partition.map.atm
.........\..............\...................\processor.root_partition.map.dpi
.........\..............\...................\processor.root_partition.map.hdbx
.........\..............\...................\processor.root_partition.map.kpt
.........\..............\README
.........\processor.asm.rpt
.........\processor.done
.........\processor.fit.rpt
.........\processor.fit.summary
.........\processor.flow.rpt
.........\processor.map.rpt
.........\processor.map.summary
.........\processor.mif
.........\processor.pin
.........\processor.pof
.........\processor.qpf
.........\processor.qsf
.........\processor.sim.rpt
.........\processor.sof
.........\processor.tan.rpt
.........\processor.tan.summary
.........\processor.v

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