Verilog SDIO RX FSM module

FSM_1\.untf
.....\automake.log
.....\FSM_1.dhp
.....\FSM_1.ise
.....\FSM_1.ise_ISE_Backup
.....\Project.dhp
.....\sdio_rx_fsm.bld
.....\sdio_rx_fsm.cel
.....\sdio_rx_fsm.cmd_log
.....\sdio_rx_fsm.lso
.....\sdio_rx_fsm.ngc
.....\sdio_rx_fsm.ngd
.....\sdio_rx_fsm.ngr
.....\sdio_rx_fsm.prj
.....\sdio_rx_fsm.stx
.....\sdio_rx_fsm.syr
.....\sdio_rx_fsm.ucf
.....\sdio_rx_fsm.v
.....\sdio_rx_fsm_summary.html
.....\sdio_rx_fsm_vhdl.prj
.....\__projnav.log
.....\.........\ednTOngd_tcl.rsp
.....\.........\FSM_1.gfl
.....\.........\FSM_1_flowplus.gfl
.....\.........\parentCreateTimingConstraintsApp_tcl.rsp
.....\.........\runXst_tcl.rsp
.....\.........\sdio_rx_fsm.xst
.....\.........\sumrpt_tcl.rsp
.....\.ngo\netlist.lst
.....\xst\work\hdllib.ref
.....\...\....\vlg09\sdio__rx__fsm.bin
LIP1742COR_sdio_rx_fsm_1.doc
LIP1742CORE_sdio_rx_fsm.doc
sdio_rx_fsm.v
FSM_1\xst\dump.xst\sdio_rx_fsm.prj\ngx\opt
.....\...\........\...............\...\notopt
.....\...\........\...............\ngx
.....\...\work\vlg09
.....\...\dump.xst\sdio_rx_fsm.prj
.....\...\work
.....\...\dump.xst
.....\__projnav
.....\_xmsgs
.....\_ngo
.....\xst
FSM_1

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