Provided by Altera SOPC technology built in EP2C8 series FPGA hardware architecture, the register does not operate through the C language, FPGA-based embedded development provides a new example of IO port operation- register operations.

NiosII_LED\.metadata\.lock
..........\.........\.log
..........\.........\.plugins\org.eclipse.cdt.core\.log
..........\.........\........\................make.core\specs.c
..........\.........\........\.........................\specs.cpp
..........\.........\........\.....................ui\dialog_settings.xml
..........\.........\........\.............ore.resources\.root\.indexes\history.version
..........\.........\........\..........................\.....\........\properties.index
..........\.........\........\..........................\.....\........\properties.version
..........\.........\........\..........................\.....\2.tree
..........\.........\........\..........................\.safetable\org.eclipse.core.resources
..........\.........\........\..................untime\.settings\org.eclipse.cdt.debug.core.prefs
..........\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
..........\.........\........\........................\.........\org.eclipse.core.resources.prefs
..........\.........\........\........................\.........\org.eclipse.ui.ide.prefs
..........\.........\........\........................\.........\org.eclipse.ui.prefs
..........\.........\........\............ui.ide\dialog_settings.xml
..........\.........\........\...............workbench\dialog_settings.xml
..........\.........\........\........................\workbench.xml
..........\.........\version.ini
..........\.sopc_builder\filters.xml
..........\.............\install.ptf
..........\.............\install2.ptf
..........\.............\preferences.xml
..........\altpllpll.cmp
..........\altpllpll.ppf
..........\altpllpll.qip
..........\altpllpll.vhd
..........\altpllpll_0.cmp
..........\altpllpll_0.ppf
..........\altpllpll_0.qip
..........\altpllpll_0.vhd
..........\altpllpll_0_wave0.jpg
..........\altpllpll_0_waveforms.html
..........\cpu.ocp
..........\cpu.sdc
..........\cpu.vhd
..........\cpu.vho
..........\cpu_bht_ram.mif
..........\cpu_dc_tag_ram.mif
..........\cpu_ic_tag_ram.mif
..........\cpu_jtag_debug_module_sysclk.vhd
..........\cpu_jtag_debug_module_tck.vhd
..........\cpu_jtag_debug_module_wrapper.vhd
..........\CPU_LED.bsf
..........\CPU_LED.html
..........\CPU_LED.ptf
..........\CPU_LED.ptf.8.0
..........\CPU_LED.ptf.bak
..........\CPU_LED.ptf.pre_generation_ptf
..........\CPU_LED.qip
..........\CPU_LED.sopc
..........\CPU_LED.sopcinfo
..........\CPU_LED.vhd
..........\CPU_LED_clock_0.vhd
..........\CPU_LED_generation_script
..........\CPU_LED_inst.vhd
..........\CPU_LED_log.txt
..........\........sim\atail-f.pl
..........\...........\cpu_bht_ram.dat
..........\...........\cpu_bht_ram.hex
..........\...........\cpu_dc_tag_ram.dat
..........\...........\cpu_dc_tag_ram.hex
..........\...........\cpu_ic_tag_ram.dat
..........\...........\cpu_ic_tag_ram.hex
..........\...........\cpu_ociram_default_contents.dat
..........\...........\cpu_ociram_default_contents.hex
..........\...........\cpu_rf_ram_a.dat
..........\...........\cpu_rf_ram_a.hex
..........\...........\cpu_rf_ram_b.dat
..........\...........\cpu_rf_ram_b.hex
..........\...........\create_CPU_LED_project.do
..........\...........\epcs_boot_rom.dat
..........\...........\epcs_boot_rom.hex
..........\...........\epcs_boot_rom.sym
..........\...........\jtag_uart_input_mutex.dat
..........\...........\jtag_uart_input_stream.dat
..........\...........\jtag_uart_log.bat
..........\...........\jtag_uart_output_stream.dat
..........\...........\list_presets.do
..........\...........\modelsim.tcl
..........\...........\sdram.dat
..........\...........\sdram.sym
..........\...........\setup_sim.do
..........\...........\virtuals.do
..........\...........\wave_presets.do
..........\cpu_mult_cell.vhd
..........\cpu_ociram_default_contents.mif
..........\cpu_oci_test_bench.vhd
..........\cpu_rf_ram_a.mif
..........\cpu_rf_ram_b.mif
..........\cpu_test_bench.vhd
..........\db\altsyncram_29f1.tdf
..........\..\altsyncram_9tl1.tdf
..........\..\altsyncram_9vc1.tdf
..........\..\altsyncram_e502.tdf
..........\..\altsyncram_ij21.tdf
....

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