可靠性的设计应用硬件连线保证握手。 以MCU+IDT7132+PC结构为例子: IDT7132两侧的BUSY线分别接到MCU的INT0中断上和PC总线的A10脚(IO-CH-RDY)上,作为MCU和计算机同时读写IDT7132 的同一个地址单元时的“忙闲”状态线。当两侧访问不同的地址单元时,BUSY线无效,两侧操作互不影响。当两侧“几乎同时”访问同一个单元时,按IDT7132的总线仲裁逻辑,对两侧的片选信号和地址信号之一到达时间间隔只要大于5ns,就能对先到达的一侧提供读写通道, 保证数据读写的真实性。 同时将另一侧的BUSY线置低, 为MCU或计算机提供中断或等待信号。众所周知,89C51不具备插入等待周期延时操作的能力。当MCU一侧先行操作时,计算机一侧的BUSY线有效,PC总线上的IO-CH-RDY状态线被拉低,命令计算机CPU插入等待周期,延时等待MCU一侧完成读写操作后,再进行读写操作。当计算机一侧占据IDT7132的一个地址单元时, MCU一侧再操作该单元,MCU读写的数据无效。我们采用了判断标志位的方式解决此问题。当对应的BUSY线变低INT0中断有效时,MCU完成该条读写指令后立即进入中断,置标志位,中断返回后,即执行查询标志位的指令同,判断此次操作是否有效。未成功,重复操作,直至读写成功。

双口RAM硬件和软件可靠性握手的实现.pdf

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