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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 753kb
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Introduction - If you have any usage issues, please Google them yourself
vhdl write 8-bits ALU, including the addition and subtraction and non-operating mode 6
Packet file list
(Preview for download)
LabALU
......\nregn
......\alu_1.01
......\aluna
......\LabALU1.0
......\LabALU_0.5
......\nregn\_xmsgs
......\.....\xst
......\.....\nregn_xdb
......\alu_1.01\_ngo
......\........\xst
......\........\_xmsgs
......\........\alu_1.01_xdb
......\...na\_ngo
......\LabALU_0.5\LabALU_0.5_xdb
......\..........\xst
......\..........\_xmsgs
......\nregn\xst\work
......\.....\...\projnav.tmp
......\.....\...\dump.xst
......\.....\nregn_xdb\tmp
......\alu_1.01\xst\dump.xst
......\........\...\file graph
......\........\...\work
......\........\...\projnav.tmp
......\........\alu_1.01_xdb\tmp
......\LabALU_0.5\LabALU_0.5_xdb\tmp
......\..........\xst\dump.xst
......\..........\...\file graph
......\..........\...\projnav.tmp
......\..........\...\work
......\nregn\xst\work\sub00
......\.....\...\dump.xst\RegN.prj
......\.....\nregn_xdb\tmp\ise
......\alu_1.01\xst\dump.xst\ALUNA.prj
......\........\...\........\LabALU.prj
......\........\...\work\sub00
......\........\alu_1.01_xdb\tmp\ise
......\LabALU_0.5\LabALU_0.5_xdb\tmp\ise
......\..........\xst\dump.xst\RegN.prj
......\..........\...\work\sub00
......\nregn\xst\dump.xst\RegN.prj\ngx
......\.....\nregn_xdb\tmp\ise\__REGISTRY__
......\.....\.........\...\...\__OBJSTORE__
......\alu_1.01\xst\dump.xst\ALUNA.prj\ngx
......\........\...\........\LabALU.prj\ngx
......\........\alu_1.01_xdb\tmp\ise\__REGISTRY__
......\........\............\...\...\__OBJSTORE__
......\LabALU_0.5\LabALU_0.5_xdb\tmp\ise\__OBJSTORE__
......\..........\..............\...\...\__REGISTRY__
......\..........\xst\dump.xst\RegN.prj\ngx
......\nregn\xst\dump.xst\RegN.prj\ngx\opt
......\.....\...\........\........\...\notopt
......\.....\nregn_xdb\tmp\ise\__REGISTRY__\_ProjRepoInternal_
......\.....\.........\...\...\............\xst
......\.....\.........\...\...\............\XSLTProcess
......\.....\.........\...\...\............\xreport
......\.....\.........\...\...\............\xpwr
......\.....\.........\...\...\............\vlogcomp
......\.....\.........\...\...\............\vhpcomp
......\.....\.........\...\...\............\tsim
......\.....\.........\...\...\............\trce
......\.....\.........\...\...\............\taengine
......\.....\.........\...\...\............\simgen
......\.....\.........\...\...\............\runner
......\.....\.........\...\...\............\ProjectNavigatorGui
......\.....\.........\...\...\............\ProjectNavigator11
......\.....\.........\...\...\............\ProjectNavigator
......\.....\.........\...\...\............\platgen
......\.....\.........\...\...\............\par
......\.....\.........\...\...\............\ngdbuild
......\.....\.........\...\...\............\ngcbuild
......\.....\.........\...\...\............\ngc2edif
......\.....\.........\...\...\............\netgen
......\.....\.........\...\...\............\map
......\.....\.........\...\...\............\libgen
......\.....\.........\...\...\............\idem
......\.....\.........\...\...\............\hprep6
......\.....\.........\...\...\............\HierarchicalDesign
......\.....\.........\...\...\............\fuse
......\.....\.........\...\...\............\dumpngdio
......\.....\.........\...\...\............\cpldfit
......\.....\.........\...\...\............\common
......\.....\.........\...\...\............\bitinit
......\.....\.........\...\...\............\bitgen
......\.....\.........\...\...\............\Autonym
......\.....\.........\...\...\..OBJSTORE__\_ProjRepoInternal_
......\.....\.........\...\...\............\xreport
......\.....\.........\...\...\............\ProjectNavigatorGui
......\.....\.........\...\...\............\ProjectNavigator11
......\.....\.........\...\...\............\ProjectNavigator
......\.....\.........\...\...\............\PnAutoRun
......\.....\.........\...\...\............\HierarchicalDesign
......\.....\.........\...\...\............\common
......\.....\.........\...\...\............\Autonym
......\alu_1.01\xst\dump.xst\ALUNA.prj\ngx\opt
......\........\...\........\.........\...\notopt
......\........\...\........\LabALU.prj\ngx\notopt
......\........\.
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