vhdl Design Example Two: Testing the order of waveform generation, the state machine instance

vhdl2\其他设计举例\4位乘法器.txt
.....\............\4位除法器.txt
.....\............\伪随机比特发生器.txt
.....\............\布斯乘法器.txt
.....\测试向量（Test Bench）和波形产生\经典双进程状态机（含test beach）.txt
.....\状态机举例\使用变量的状态机.txt
.....\..........\带同步复位的状态机.txt
.....\..........\带莫尔米勒输出的状态机.txt
.....\..........\米勒型状态机.txt
.....\..........\莫尔型状态机1.txt
.....\..........\莫尔型状态机2.txt
.....\其他设计举例
.....\测试向量（Test Bench）和波形产生
.....\状态机举例
vhdl2

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