Verilog Debug interface code

vsim.wlf
work\_info
....\dbg_trace\verilog.psm
....\.........\_primary.dat
....\.........\_primary.vhd
....\.....op\verilog.psm
....\.......\_primary.dat
....\.......\_primary.vhd
....\....sync_clk1_clk2\verilog.psm
....\..................\_primary.dat
....\..................\_primary.vhd
....\....registers\verilog.psm
....\.............\_primary.dat
....\.............\_primary.vhd
....\............\verilog.psm
....\............\_primary.dat
....\............\_primary.vhd
....\....crc8_d1\verilog.psm
....\...........\_primary.dat
....\...........\_primary.vhd
dbg_crc8_d1.v
dbg_defines.v
dbg_register.v
dbg_registers.v
dbg_sync_clk1_clk2.v
dbg_timescale.v
dbg_top.v
dbg_trace.v
dbgsupp.pdf
do.do
file.do
readme.txt
run_dbg.do
transcript
work\dbg_trace
....\dbg_top
....\dbg_sync_clk1_clk2
....\dbg_registers
....\dbg_register
....\dbg_crc8_d1
work

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