This tutorial is a part of a series of tutorials provided by Xilinx to lead the user through the Xilinx FPGA Design Flow. This archive contains the necessary design files to perform the tutorial.

src
...\cnt60.vhd
...\decode.vhd
...\hex2led.vhd
...\smallcntr.vhd
...\statmach.vhd
...\stopwatch.vhd
...\testbench.vhd
...\rtl_sim.do
...\stim.do
...\time_sim.do
watch
soln
....\time
....\....\time_sim.sdf
....\....\time_sim.vhd
....\....\time_sim.do
....\....\testbench.vhd
....\func
....\....\statmach.vhd
....\....\stopwatch.vhd
....\....\testbench.vhd
....\....\decode.vhd
....\....\rtl_sim.do
....\....\smallcntr.vhd
....\....\cnt60.vhd
....\....\hex2led.vhd
....\....\work
....\....\....\_info
....\....\....\smallcntr
....\....\....\.........\_primary.dat
....\....\....\.........\inside.dat
....\....\....\.........\inside.asm
....\....\....\cnt60
....\....\....\.....\_primary.dat
....\....\....\.....\inside.dat
....\....\....\.....\inside.asm
....\....\....\decode
....\....\....\......\_primary.dat
....\....\....\......\behavioral.dat
....\....\....\......\behavioral.asm
....\....\....\hex2led
....\....\....\.......\_primary.dat
....\....\....\.......\hex2led_arch.dat
....\....\....\.......\hex2led_arch.asm
....\....\....\statmach
....\....\....\........\_primary.dat
....\....\....\........\behavior.dat
....\....\....\........\behavior.asm
....\....\....\stopwatch
....\....\....\.........\_primary.dat
....\....\....\.........\inside.dat
....\....\....\.........\inside.asm
....\....\....\cfg_tenths
....\....\....\..........\_primary.dat
....\....\....\..........\_vhdl.asm
....\....\....\testbench
....\....\....\.........\_primary.dat
....\....\....\.........\testbench_arch.dat
....\....\....\.........\testbench_arch.asm
....\....\....\stopwatch_cfg
....\....\....\.............\_primary.dat
....\....\....\.............\_vhdl.asm
....\....\stim.do
....\....\stopwatch.edf
....\....\xproj
....\....\.....\stopwatch.xpj
....\....\.....\ver1
....\....\.....\....\version.vbf
....\....\.....\....\rev1
....\....\.....\....\....\revision.obf
....\....\.....\....\....\revision.rbf
....\....\.....\....\....\stopwatch.ucf
....\....\.....\....\....\virtex.imp
....\....\.....\....\....\virtex.cfg
....\....\.....\....\....\command.his
....\....\.....\....\....\program.his
....\....\.....\....\....\stopwatch.bld
....\....\.....\....\....\fe.log
....\....\.....\....\....\rptbrwsr.dat
....\....\.....\....\....\stopwatch.ngd
....\....\.....\....\....\map.mrp
....\....\.....\....\....\virtex.sml
....\....\.....\....\....\map.ngm
....\....\.....\....\....\map.ncd
....\....\.....\....\....\stopwatch.pcf
....\....\.....\....\....\stopwatch.par
....\....\.....\....\....\stopwatch.ncd
....\....\.....\....\....\stopwatch.xpi
....\....\.....\....\....\stopwatch.dly
....\....\.....\....\....\stopwatch.pad
....\....\.....\....\....\stopwatch.twr
....\....\.....\....\....\stopwatch.alf
....\....\.....\....\....\stopwatch.nga
....\....\.....\....\....\time_sim.sdf
....\....\.....\....\....\time_sim.vhd
....\....\.....\....\....\ngd2vhdl.log
....\....\.....\....\....\bitgen.ut
....\....\.....\....\....\stopwatch.bgn
....\....\.....\....\....\stopwatch.drc

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