A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project

ddr2_test\ddr_test.qpf
.........\ddr_test.qsf
.........\ddr_test.map.summary
.........\ddr2_pre_compile_ddr_timing_summary.txt
.........\auto_verify_ddr_timing.tcl
.........\ddr_lib_path.tcl
.........\auto_add_ddr_constraints.tcl
.........\ddr2.qip
.........\ddr_pll_stratixii.v
.........\ddr_pll_stratixii.ppf
.........\ddr_pll_stratixii.bsf
.........\ddr_pll_stratixii_bb.v
.........\ddr_pll_stratixii.qip
.........\ddr2.html
.........\ddr_test.done
.........\pll_waveforms.html
.........\pll_wave0.jpg
.........\pll.ppf
.........\pll.v
.........\pll.bsf
.........\pll_bb.v
.........\pll.qip
.........\ddr_test.map.smsg
.........\remove_add_constraints_for_ddr2.tcl
.........\ddr_test.dpf
.........\ddr_test.pin
.........\ddr_test.fit.smsg
.........\ddr_test.fit.summary
.........\ddr_test_time_limited.sof
.........\ddr_test.jdi
.........\ddr_test.tan.summary
.........\ddr2_post_summary.txt
.........\ddr2_extraction_log.txt
.........\ddr2_extraction_failures.txt
.........\extraction_min_allnodes.txt
.........\extraction_max_allnodes.txt
.........\ddr2_extraction_data.txt
.........\ddr2_EP2S90_stratixii-c4_paths.txt
.........\ddr2_estimated_data.dat
.........\ddr2_extraction_log2.txt
.........\ddr2.v
.........\ddr2_bb.v
.........\ddr2.bsf
.........\ddr2_ddr_settings.txt
.........\ddr2_auk_ddr_sdram.v
.........\ddr2_auk_ddr_dll.v
.........\ddr_test_1.v
.........\ddr2_auk_ddr_clk_gen.v
.........\ddr2_auk_ddr_datapath.v
.........\ddr2_auk_ddr_dqs_group.v
.........\verify_timing_for_ddr2.tcl
.........\add_constraints_for_ddr2.tcl
.........\constraints_out.txt
.........\ddr2.ppf
.........\rom_waveforms.html
.........\rom_wave0.jpg
.........\rom.v
.........\rom.bsf
.........\rom_bb.v
.........\rom.qip
.........\counter_waveforms.html
.........\counter_wave0.jpg
.........\counter.v
.........\counter.bsf
.........\counter_bb.v
.........\counter.qip
.........\rom_wave1.jpg
.........\ddr_test.mif
.........\ddr2_example_driver.v
.........\ddr_test.fit.rpt
.........\ddr_test.asm.rpt
.........\ddr_test.tan.rpt
.........\stp1.stp
.........\ddd_pll_waveforms.html
.........\ddd_pll_wave0.jpg
.........\ddd_pll.ppf
.........\ddd_pll.v
.........\ddd_pll.bsf
.........\ddd_pll_bb.v
.........\ddd_pll.qip
.........\ddr_test.v.bak
.........\ddr_test.v
.........\ddr_test.map.rpt
.........\ddr_test.flow.rpt
.........\ddr_test.qws
.........\...2_test_2\ddr_test.qpf
.........\...........\ddr_test.qsf
.........\...........\ddr_test.map.summary
.........\...........\ddr2_pre_compile_ddr_timing_summary.txt
.........\...........\auto_verify_ddr_timing.tcl
.........\...........\ddr_lib_path.tcl
.........\...........\auto_add_ddr_constraints.tcl
.........\...........\ddr2.qip
.........\...........\ddr_pll_stratixii.v
.........\...........\ddr_pll_stratixii.ppf
.........\...........\ddr_pll_stratixii.bsf
.........\...........\ddr_pll_stratixii_bb.v
.........\...........\ddr_pll_stratixii.qip
.........\...........\ddr2.html
.........\...........\ddr_test.done

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