spartan-3a ddr2 read and write control of the source, there are versions of verilog and vhdl

ssss\ddr2_sdram\folder_details.txt
....\..........\verilog\vlog_bl8\example_design\datasheet.txt
....\..........\.......\........\..............\design_testing.txt
....\..........\.......\........\..............\par\create_ise.bat
....\..........\.......\........\..............\...\icon_coregen.xco
....\..........\.......\........\..............\...\ila_coregen.xco
....\..........\.......\........\..............\...\ise_flow.bat
....\..........\.......\........\..............\...\ise_run.txt
....\..........\.......\........\..............\...\makeproj.bat
....\..........\.......\........\..............\...\mem_interface_top.ut
....\..........\.......\........\..............\...\readme.txt
....\..........\.......\........\..............\...\set_ise_prop.tcl
....\..........\.......\........\..............\...\vio_coregen.xco
....\..........\.......\........\..............\...\vlog_bl8.bit
....\..........\.......\........\..............\...\vlog_bl8.cdc
....\..........\.......\........\..............\...\vlog_bl8.ucf
....\..........\.......\........\..............\rtl\vlog_bl8.v
....\..........\.......\........\..............\...\vlog_bl8_addr_gen_0.v
....\..........\.......\........\..............\...\vlog_bl8_cal_ctl.v
....\..........\.......\........\..............\...\vlog_bl8_cal_top.v
....\..........\.......\........\..............\...\vlog_bl8_clk_dcm.v
....\..........\.......\........\..............\...\vlog_bl8_cmd_fsm_0.v
....\..........\.......\........\..............\...\vlog_bl8_cmp_data_0.v
....\..........\.......\........\..............\...\vlog_bl8_controller_0.v
....\..........\.......\........\..............\...\vlog_bl8_controller_iobs_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_gen_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_path_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_path_iobs_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_read_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_read_controller_0.v
....\..........\.......\........\..............\...\vlog_bl8_data_write_0.v
....\..........\.......\........\..............\...\vlog_bl8_dqs_delay.v
....\..........\.......\........\..............\...\vlog_bl8_fifo_0_wr_en_0.v
....\..........\.......\........\..............\...\vlog_bl8_fifo_1_wr_en_0.v
....\..........\.......\........\..............\...\vlog_bl8_infrastructure.v
....\..........\.......\........\..............\...\vlog_bl8_infrastructure_iobs_0.v
....\..........\.......\........\..............\...\vlog_bl8_infrastructure_top.v
....\..........\.......\........\..............\...\vlog_bl8_iobs_0.v
....\..........\.......\........\..............\...\vlog_bl8_main_0.v
....\..........\.......\........\..............\...\vlog_bl8_parameters_0.v
....\..........\.......\........\..............\...\vlog_bl8_ram8d_0.v
....\..........\.......\........\..............\...\vlog_bl8_ram8d_1.v
....\..........\.......\........\..............\...\vlog_bl8_rd_gray_cntr.v
....\..........\.......\........\..............\...\vlog_bl8_s3_dm_iob.v
....\..........\.......\........\..............\...\vlog_bl8_s3_dqs_iob.v
....\..........\.......\........\..............\...\vlog_bl8_s3_dq_iob.v
....\..........\.......\........\..............\...\vlog_bl8_tap_dly.v
....\..........\.......\........\..............\...\vlog_bl8_test_bench_0.v
....\..........\.......\........\..............\...\vlog_bl8_top_0.v
....\..........\.......\........\..............\...\vlog_bl8_wr_gray_cntr.v
....\..........\.......\........\..............\sim\ddr2_model.v
....\..........\.......\........\..............\...\ddr2_model_parameters.vh
....\..........\.......\........\..............\...\glbl.v
....\..........\.......\........\..............\...\sim.do
....\..........\.......\........\..............\...\sim_tb_top.v
....\..........\.......\........\..............\...\wiredly.v
....\..........\.......\........\..............\.ynth\mem_interface_top_synp.sdc
....\..........\.......\........\..............\.....\scri

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