Using Xilinx' s FPGA, Verilog HDL language used to send and receive serial data.

serial_communication\.recordref
....................\baud_generator.edn
....................\baud_generator.fse
....................\baud_generator.ise_created
....................\baud_generator.ncf
....................\baud_generator.prj
....................\baud_generator.sdc
....................\baud_generator.srd
....................\baud_generator.srm
....................\baud_generator.srr
....................\baud_generator.srs
....................\baud_generator.tlg
....................\baud_generator.v
....................\baud_generator_compile.tcl
....................\baud_generator_map.tcl
....................\baud_generator_summary.html
....................\receive.fse
....................\receive.v
....................\rpt_baud_generator.areasrr
....................\rpt_baud_generator_areasrr.htm
....................\rpt_receive_areasrr.htm
....................\rpt_transmit.areasrr
....................\rpt_transmit_areasrr.htm
....................\serial_communication.ise
....................\serial_communication.ise_ISE_Backup
....................\stdout.log
....................\transmit.edn
....................\transmit.fse
....................\transmit.ise_created
....................\transmit.ncf
....................\transmit.prj
....................\transmit.sdc
....................\transmit.srd
....................\transmit.srm
....................\transmit.srr
....................\transmit.srs
....................\transmit.tlg
....................\transmit.v
....................\transmit_compile.tcl
....................\transmit_map.tcl
....................\transmit_summary.html
....................\traplog.tlg
....................\uart_top.fse
....................\uart_top.ise_created
....................\uart_top.prj
....................\uart_top.sdc
....................\uart_top.srr
....................\uart_top.srs
....................\uart_top.tlg
....................\uart_top.v
....................\uart_top_compile.tcl
....................\uart_top_map.tcl
....................\uart_top_summary.html
....................\__ISE_repository_serial_communication.ise_.lock
....................\verif\baud_generator.vif
....................\.....\receive.vif
....................\.....\transmit.vif
....................\.....\uart_top.vif
....................\syntmp\baud_generator.msg
....................\......\baud_generator.plg
....................\......\receive.msg
....................\......\receive.plg
....................\......\transmit.msg
....................\......\transmit.plg
....................\......\uart_top.msg
....................\......\uart_top.plg
....................\_xmsgs
....................\verif
....................\syntmp
serial_communication

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