实现16位加法器功能，使用Verilog语言编程，使用的是数据流形式

adder_16\full_adder_16.v
........\full_adder_16_tb.v
........\test.cr.mti
........\test.mpf
........\vsim.wlf
........\work\@add_full_@a@s@i@c\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\.....half_@a@s@i@c\verilog.asm
........\....\..................\_primary.dat
........\....\..................\_primary.vhd
........\....\full_adder_16\verilog.asm
........\....\.............\_primary.dat
........\....\.............\_primary.vhd
........\....\............._tb\verilog.asm
........\....\................\_primary.dat
........\....\................\_primary.vhd
........\....\_info
........\....\@add_full_@a@s@i@c
........\....\@add_half_@a@s@i@c
........\....\full_adder_16
........\....\full_adder_16_tb
........\work
adder_16

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