this is a verilog code for 4 to 16 decoder

decoder4to16\automake.log
............\decoder3to8.ldo
............\decoder3to8.lso
............\decoder3to8.prj
............\decoder3to8.stx
............\decoder3to8_vhdl.prj
............\decoder4to16.dhp
............\decoder4to16.ise
............\decoder4to16.ise_ISE_Backup
............\decodr4to16.ldo
............\decodr4to16.lso
............\decodr4to16.prj
............\decodr4to16.stx
............\decodr4to16.v
............\decodr4to16_vhdl.prj
............\prjname.lso
............\Project.dhp
............\transcript
............\vsim.wlf
............\wave.do
............\.ork\decoder3to8\verilog.psm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\.....r4to16\verilog.psm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\glbl\verilog.psm
............\....\....\_primary.dat
............\....\....\_primary.vhd
............\....\_info
............\xst\work\hdllib.ref
............\...\....\vlg00\decoder3to8.bin
............\...\....\...5B\decodr4to16.bin
............\__projnav\decoder3to8.xst
............\.........\decoder4to16.gfl
............\.........\decoder4to16_flowplus.gfl
............\.........\decodr4to16.xst
............\.........\xst_sprjTOstx_tcl.rsp
............\__projnav.log
............\xst\work\vlg00
............\...\....\vlg5B
............\work\decoder3to8
............\....\decodr4to16
............\....\glbl
............\xst\work
............\work
............\xst
............\_xmsgs
............\__projnav
decoder4to16

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