It designs a clock by Verilog

alarm\alarm_block.v
.....\alarm_block.v.bak
.....\alarm_counter.v
.....\alarm_counter.v.bak
.....\alarm_jh.cr.mti
.....\alarm_jh.mpf
.....\alarm_sm_2.v
.....\alarm_sm_2.v.bak
.....\alarm_state_machine.v
.....\alarm_state_machine.v.bak
.....\comparator.v
.....\comparator.v.bak
.....\convertor.v
.....\convertor.v.bak
.....\convertor_ckt.v
.....\convertor_ckt.v.bak
.....\lab\ALARM_BLOCK.v
.....\...\ALARM_COUNTER.v
.....\...\ALARM_SM_2.v
.....\...\ALARM_STATE_MACHINE.v
.....\...\COMPARATOR.v
.....\...\CONVERTOR.pla
.....\...\CONVERTOR_CKT.v
.....\...\HOURS_FILTER.v
.....\...\lab.cr.mti
.....\...\lab.mpf
.....\...\mux.v
.....\...\mux.v.bak
.....\...\TIME_BLOCK.v
.....\...\TIME_COUNTER.v
.....\...\TIME_STATE_MACHINE.v
.....\...\top.v
.....\...\work\@a@l@a@r@m_@s@m_2\verilog.psm
.....\...\....\.................\_primary.dat
.....\...\....\.................\_primary.dbs
.....\...\....\.................\_primary.vhd
.....\...\....\.c@o@m@p@a@r@a@t@o@r\verilog.psm
.....\...\....\....................\_primary.dat
.....\...\....\....................\_primary.dbs
.....\...\....\....................\_primary.vhd
.....\...\....\.....n@v@e@r@t@o@r_@c@k@t\verilog.psm
.....\...\....\.........................\_primary.dat
.....\...\....\.........................\_primary.dbs
.....\...\....\.........................\_primary.vhd
.....\...\....\.h@o@u@r@s_@f@i@l@t@e@r\verilog.psm
.....\...\....\.......................\_primary.dat
.....\...\....\.......................\_primary.dbs
.....\...\....\.......................\_primary.vhd
.....\...\....\.m@u@x\verilog.psm
.....\...\....\......\_primary.dat
.....\...\....\......\_primary.dbs
.....\...\....\......\_primary.vhd
.....\...\....\.t@o@p\verilog.psm
.....\...\....\......\_primary.dat
.....\...\....\......\_primary.dbs
.....\...\....\......\_primary.vhd
.....\...\....\_info
.....\...\....\_vmake
.....\.ixiaoming\ALARM_BLOCK.v
.....\..........\ALARM_BLOCK_tb.v
.....\..........\ALARM_COUNTER.v
.....\..........\ALARM_SM_2.V
.....\..........\ALARM_SM_2_tb.v
.....\..........\ALARM_STATE_MACHINE.v
.....\..........\COMPARATOR.v
.....\..........\COMPARATOR_tb.v
.....\..........\CONVERTOR_CKT.v
.....\..........\CONVERTOR_CKT.v.bak
.....\..........\CONVERTOR_CKT_tb.v
.....\..........\MUX.V
.....\..........\MUX_tb.v
.....\..........\SEVEN_SEG_CONVERTOR.v
.....\..........\TIME_BLOCK.v
.....\..........\TIME_BLOCK_tb.v
.....\..........\TIME_COUNTER.v
.....\..........\TIME_STATE_MACHINE.v
.....\..........\TOP.v
.....\..........\TOP.v.bak
.....\..........\TOP_tb.v
.....\..........\transcript
.....\..........\work\_info
.....\..........\xiaoming.cr.mti
.....\..........\xiaoming.mpf
.....\mux.v
.....\mux.v.bak
.....\sev_convertor.v.bak
.....\testb_alarm_block.v
.....\testb_alarm_block.v.bak
.....\testb_alarm_sm_2.v
.....\testb_time_block.v
.....\testb_time_block.v.bak
.....\time_block.v
.....\time_block.v.bak
.....\time_counter.v
.....\time_counter.v.bak
.....\time_state_machine.v
.....\time_state_machine.v.bak
.....\transcript
.....\vsim.wlf
.....\work\alarm_block\verilog.psm

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